Patent Assignment
Reel/Frame 054371/0684
Release of Security Interest
Recorded: 2020-11-10
Pages: 75
Assignor
CPPIB CREDIT INVESTMENTS INC.
Executed: 2020-10-28
Assignee
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
515 LEGGET DRIVE, SUITE 704, OTTAWA, K2K 3G4, CANADA
Covered Properties
(85)
Method and System for State-Dependent Admission Control and Routing of Multi-Rate Circuit-Switched Traffic
Patent:
6,366,559 →
Application:
09/092,732 →
Synchronous Dynamic Random Access Memory in a Semiconductor Memory Device
Patent:
6,064,619 →
Application:
09/106,308 →
Method for Manufacturing a Capacitor of a Semiconductor Device
Patent:
6,066,540 →
Application:
09/143,096 →
Method and Apparatus for Connecting Network Segments
Patent:
6,483,852 →
Application:
09/210,456 →
Plural Memory Banks Memory Device That Can Simultaneously Read from or Write to All of the Memory Banks During Testing
Patent:
6,198,667 →
Application:
09/290,399 →
System for Transmitting Messages to Improved Stations, and Corresponding Processing
Patent:
6,697,379 →
Application:
09/312,486 →
Sense Amplifier Driving Device
Patent:
6,144,230 →
Application:
09/317,113 →
Trench Isolation Method
Patent:
6,255,194 →
Application:
09/324,919 →
Tungsten Layer Formation Method for Semiconductor Device and Semiconductor Device Using the Same
Patent:
6,579,794 →
Application:
09/357,126 →
Wiring Structure of Semiconductor Device and Method for Manufacturing the Same
Patent:
6,355,515 →
Application:
09/359,243 →
Method for Fabricating Contact Pad for Semiconductor Device
Patent:
6,297,091 →
Application:
09/397,136 →
Analog Mixed Digital Dll
Patent:
6,392,456 →
Application:
09/427,272 →
A Semiconductor Memory Array Layout
Patent:
6,329,678 →
Application:
09/451,852 →
Apparatus and Method for Performing Data Read Operation in Ddr Sdram
Patent:
6,201,760 →
Application:
09/461,718 →
Tungsten layer formation method for semiconductor device and semiconductor device using the same
Patent:
6,404,054 →
Application:
09/609,927 →
Adaptive Layered Coding for Voice Over Wireless Ip Applications
Patent:
6,434,191 →
Application:
09/653,913 →
Method for fabricating a semiconductor memory device
Patent:
6,350,650 →
Application:
09/710,958 →
Interface Circuit for Using in High-Speed Semiconductor Device and Interfacing Method
Delay Locked Loop for Use in Semiconductor Memory Device
Delay Locked Loop with Delay Control Unit for Noise Elimination
Column Transistor for Semiconductor Devices
Semiconductor Memory Device Having a Plurality of Banks Sharing a Column Control Unit
Method and Systems for Bandwidth Management in Packet Data Networks
Sense Amplifier Circuit for Use in a Semiconductor Memory Device
Method for Making High K Dielectric Gate for Semiconductor Device
Transfer Circuit of Semiconductor Device and Structure Thereof
Method of Forming Dual-Metal Gates in Semiconductor Device
Nonvolatile Semiconductor Memory Device Having Changeable Spare Memory Address
Wiring Structure of Semiconductor Device
Circuit for Generating Internal Address in Semiconductor Memory Device
Method of Forming a Metal Gate in a Semiconductor Device Using Atomic Layer Deposition Process
Capacitor of an Integrated Circuit Device and Method of Manufacturing the Same
Memory System Capable of Increasing Utilization Efficiency of Semiconductor Memory Device and Method of Refreshing the Semiconductor Memory Device
Methods of Forming Iintegrated Circuit Devices Having a Metal-Insulator-Metal (Mim) Capacitor
Method of Forming Contact Holes in Semiconductor Devices and Method of Forming Capacitors Using the Same
Non-Volatile Semiconductor Memory Device Having Shared Row Selection Circuit
Damascene Capacitor Formed in Metal Interconnection Layer
Method and Apparatus for Optimizing Performance and Battery Life of Electronic Devices Based on System and Application Parameters
Patent:
7,111,179 →
Application:
10/268,914 →
Gate Structure with High K Dielectric
Etching Method in a Semiconductor Processing and Etching System for Performing the Same
Semiconductor Memory Device with Modified Global Input/Output Scheme
Method and System for Design and Routing in Transparent Optical Networks
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Semiconductor Device and Method for Fabricating the Same
Flash Memory Device Capable of Preventing Program Disturbance According to Partial Programming
Data Driving Circuit and Semiconductor Memory Device Having the Same
Delay Stage Insensitive to Operating Voltage and Delay Circuit Including the Same
Semiconductor Memory Device Having Row Path Control Circuit and Operating Method Thereof
On Die Termination Mode Transfer Circuit in Semiconductor Memory Device and Its Method
Redundancy Circuit in Semiconductor Memory Device Having a Multiblock Structure
Input Signal Receiving Device of Semiconductor Memory Unit
Packet Addressing Programmable Dual Port Memory Devices and Related Methods
Multi-Level High Voltage Generator
Semiconductor Devices Having a Pocket Line and Methods of Fabricating the Same
Nonvolatile Semiconductor Memory Device with Scalable Two Transistor Memory Cells
Non-Volatile Semiconductor Memory Device Having Sense Amplifier with Increased Speed
Semiconductor Memory Device with Cylindrical Storage Electrode and Method of Manufacturing the Same
Semiconductor Memory Device
Method of Forming an Interconnection Line in a Semiconductor Device
High Voltage Generator Circuit with Ripple Stabilization Function
Delay Locked Loop and Locking Method Thereof
Patent:
6,943,602 →
Application:
11/026,970 →
Fixed Offset Digital-to-Analog Conversion Device and Method
Duty Cycle Correction Circuit for Use in a Semiconductor Device
Circuit and Method for Generating Wordline Voltage in Nonvolatile Semiconductor Memory Device
Method for Forming Storage Node of Capacitor in Semiconductor Device
Method for Fabricating a Semiconductor Device
Transistor of Semiconductor Memory Device
Five Channel Fin Transistor and Method for Fabricating the Same
Semiconductor Memory Device Sharing a Data Line Sense Amplifier and a Write Driver in Order to Reduce a Chip Size
Method for Fabricating Semiconductor Device Having Capacitor
Method for Forming Storage Node of Capacitor in Semiconductor Device
Semiconductor Devices Having a Contact Plug and Fabrication Methods Thereof
Semiconductor Device with Recess and Fin Structure
Method for Manufacturing a Transistor of a Semiconductor Memory Device
Semiconductor Memory Device and Driving Method Thereof
Data Bus Line Control Circuit
Patent:
44,051 →
Application:
13/335,207 →
Method of Manufacturing Semiconductor Device with Recess and Fin Structure
Clock Control Device for Toggling an Internal Clock of a Synchronous Dram for Reduced Power Consumption
Patent:
44,590 →
Application:
13/369,988 →
Duty Cycle Correction Circuit of Delay Locked Loop and Delay Locked Loop Having the Duty Cycle Correction Circuit
Patent:
45,247 →
Application:
13/405,703 →
Dynamic Traffic Rearrangement and Restoration for Mpls Networks with Differentiated Services Capabilities
Semiconductor Memory Device and Driving Method Thereof
Patent:
44,632 →
Application:
13/538,130 →
Method of Forming a Contact Plug for a Semiconductor Device
Patent:
45,232 →
Application:
13/568,920 →
Method for Manufacturing a Transistor of a Semiconductor Memory Device
Patent:
44,532 →
Application:
13/586,272 →
Semiconductor Devices Having a Contact Plug and Fabrication Methods Thereof
Application:
13/593,655 →
Method for Manufacturing a Transistor of a Semiconductor Memory Device
Related Assignments
(11)
Other recorded transfers of the patents in this record — the chain of ownership.
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Change of Name
Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
Change of Name
Mar 13, 2014
From: 658868 N.B. INC.
To: CONVERSANT IP N.B. 868 INC.
Reel/Frame 032439/0547 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
Change of Address
Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
Assignment of Assignor's Interest
Jul 22, 2015
From: CONVERSANT IP N.B. 868 INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 036159/0386 →
Amended and Restated U.S. Patent Security Agreement (for Non-U.S. Grantors)
Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →
Change of Name
Oct 19, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 058297/0853 →
Corrective Assignment to Correct the Conveying Party's Name Previously Recorded on Reel 058297 Frame 0853. Assignor(S) Hereby Confirms the Change of Name.
Aug 28, 2023
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 064742/0953 →