Method of forming an interconnection line in a semiconductor device
View Patent ↗A method of forming an interconnection line in a semiconductor device includes forming an interlayer insulating layer on an underlying layer having a lower conductive layer, patterning the interlayer insulating layer to form an opening exposing the lower conductive layer, forming an additional material layer conformally on the underlying layer including the opening, anisotropically etching the additional material layer to form an opening spacer covering a sidewall of the opening, performing a wet etch process using the opening spacer as an etch mask, forming a conductive layer pattern in the opening, and performing a heat treatment on the opening spacer.
1. A method of forming an interconnection line in a semiconductor device, comprising:
forming an interlayer insulating layer on an underlying layer having a lower conductive layer;
patterning the interlayer insulating layer to form an opening exposing the lower conductive layer;
forming an additional material layer conformally on the underlying layer including the opening;
anisotropically etching the additional material layer to form an opening spacer covering a sidewall of the opening;
performing a wet etch process using the opening spacer as an etch mask;
forming a conductive layer pattern in the opening; and
performing a heat treatment on the opening spacer, wherein the heat treatment is performed at a temperature of at least about 700° C.
2. The method as claimed in claim 1 , wherein the interlayer insulating layer is a dielectric layer having a low dielectric constant.
3. The method as claimed in claim 1 , wherein the interlayer insulating layer is a borophosphosilicate glass (BPSG) layer.
4. The method as claimed in claim 1 , wherein the additional material layer is formed of material layer having a lower etch rate than that of the interlayer insulating layer.
5. The method as claimed in claim 1 , wherein the additional material layer is a silicon nitride layer.
6. The method as claimed in claim 1 , wherein the additional material layer is formed to have a thickness of about 100 Å or less.
7. The method as claimed in claim 1 , wherein the heat treatment is performed at a temperature of at least about 700° C. in an oxygen atmosphere.
8. The method as claimed in claim 1 , wherein the conductive layer pattern is formed of tungsten or polysilicon.
9. The method as claimed in claim 1 , wherein forming the conductive layer pattern comprises:
forming a conductive layer to fill the opening after performing the wet etch process; and
planarizing the conductive layer to expose the interlayer insulating layer.
10. The method as claimed in claim 1 , wherein the opening is a contact hole or a groove.
11. The method as claimed in claim 1 , wherein the opening is a dual damascene pattern and the additional material layer is conformally formed on the underlying layer including the dual damascene pattern.
12. The method as claimed in claim 11 , wherein the interlayer insulating layer is a dielectric layer having a low dielectric constant.
13. The method as claimed in claim 11 , wherein the interlayer insulating layer is a borophosphosilicate glass (BPSG) layer.
14. The method as claimed in claim 11 , wherein the additional material layer is formed of a material layer having a lower etch rate than that of the interlayer insulating layer.
15. The method as claimed in claim 11 , wherein the additional material layer is a silicon nitride layer.
16. The method as claimed in claim 11 , wherein the additional material layer is formed to have a thickness of about 100 Å or less.
17. The method as claimed in claim 11 , wherein the heat treatment is performed at a temperature of at least about 700° C. in an oxygen atmosphere.
18. A method of forming a semiconductor device, comprising:
providing a substrate having a first conductive feature therein;
patterning a insulating layer on the substrate so as to form an opening exposing the conductive feature;
depositing a first material layer along sidewalls of the opening, the first material layer having a first dielectric constant;
performing a first etch process on the substrate, wherein the insulating layer is susceptible to the first etch process and the first material layer protects sidewalls of the opening against the first etch process;
depositing a conductive material in the opening so as to form a second conductive feature in electrical contact with the first conductive feature; and
converting at least a portion of the first material layer to a second material, the second material having a second dielectric constant lower than the first dielectric constant.
19. The method as claimed in claim 18 , wherein the first material layer is a silicon nitride material layer and the second material is silicon oxynitride or silicon oxide.
20. The method as claimed in claim 18 , wherein converting at least a portion of the first material layer to the second material includes oxidizing the first material layer.
21. The method as claimed in claim 20 , wherein converting at least a portion of the first material layer to the second material includes heating the first material layer to a temperature greater than about 700° C.
22. The method as claimed in claim 21 , wherein converting at least a portion of the first material layer to the second material includes heating the first material layer to a temperature greater than about 700° C. in an oxygen atmosphere.