Method for fabricating semiconductor device having capacitor
View Patent ↗A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer; forming a second etch stop layer over a top electrode of the capacitor; forming a fourth insulation layer over the third insulation layer and the second etch stop layer; and performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level;
forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer;
forming a second etch stop layer over a top electrode of the capacitor;
forming a fourth insulation layer over the third insulation layer and the second etch stop layer; and
performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.
2. The method of claim 1 , wherein the performing of the plurality of etch steps includes:
performing a first etch step to etch the fourth insulation layers, the first etch step exposing a portion of the second etch stop layer and a portion of the third insulation layer;
performing a second etch step to etch the exposed portion of the third insulation layer, the second etch step exposing a portion of the first etch stop layer;
performing a third etch step to etch the exposed portion of the first etch stop layer, the third etch step exposing the upper surface of the bit line; and
performing a fourth etch step to etch the exposed portion of the second etch stop until the upper surface of the capacitor is exposed.
3. The method of claim 2 , wherein the four etch steps are performed using the same etch mask.
4. The method of claim 2 , wherein the first, third, and fourth insulation layers each includes an oxide-based material, wherein at least one etching step uses a mixture gas of C 4 F 8 , CH 2 F 2 , O 2 , and Ar.
5. The method of claim 1 , wherein the plurality of etch steps are performed using the same etch mask.
6. The method of claim 1 , wherein the second etch stop layer includes one selected from a group consisting of an amorphous silicon layer, a non-conductive polysilicon layer and a conductive silicon germanium layer.
7. The method of claim 1 , wherein the upper surface of the capacitor includes titanium nitride (TiN), wherein the second etch stop layer is etched using a mixture gas of Cl 2 and O 2 .
8. A method for fabricating a semiconductor device, comprising:
providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level, wherein first, second, and third insulation layers are formed over the bit line, the second insulation layer being a first etch stop layer;
forming a second etch stop layer over a top electrode of the capacitor;
forming a fourth insulation layer over the third insulation layer and the second etch stop layer;
etching the fourth insulation layer to expose a portion of the second etch stop layer and a portion of the third insulation layer;
etching the third insulation layer until the first etch stop layer is exposed;
etching the first etch stop layer and the first insulation layer until an upper surface of the bit line is exposed using an etch gas having high selectivity to the second etch stop layer; and
etching the second etch stop layer until the top electrode is exposed using an etch gas having high selectivity to the top electrode.
9. The method of claim 8 , wherein the second etch stop layer includes one selected from a group consisting of an amorphous silicon layer, a non-conductive polysilicon layer, and a conductive silicon germanium layer.
10. The method of claim 9 , wherein each of the first, third, and fourth insulation layers includes an oxide-based material.
11. The method of claim 10 , wherein the etching of the fourth insulation layer and the etching of the first insulation layer each uses a mixture gas of C 4 F 8 , CH 2 F 2 , O 2 , and Ar.
12. The method of claim 11 , wherein the etching of the fourth insulation layer comprises over etching the fourth insulation layer with an over etching ratio of approximately 30% or higher.
13. The method of claim 10 , wherein the first etch stop layer includes a nitride-based material.
14. The method of claim 13 , wherein the etching of the third insulation layer uses a mixture gas of C 4 F 6 , O 2 , and Ar.
15. The method of claim 9 , wherein the top electrode includes TiN.
16. The method of claim 15 , wherein the etching of the second etch stop layer comprises using a mixture gas of Cl 2 and O 2 .
17. The method of claim 16 , wherein the etching of the fourth insulation layer, the etching of the third insulation layer, the etching of the first insulation layer, and the etching of the second etch stop layer are all done using the same etch mask.
18. The method of claim 16 , further comprising a cleaning process after the etching of the third insulation layer.