Five channel fin transistor and method for fabricating the same
View Patent ↗A semiconductor device comprises a substrate defining a recessed active region and a fin active region connected to the recessed active region and extending above the recessed active region. The fin active region includes first, second, third, fourth, and fifth sides. The first and second sides are proximate the recessed active region. The fifth side is an upper side of the fin active region. The third side is provided between the first side and the fifth side. The fourth side is provided between the second side and the fifth side. A gate insulation layer is formed over the first, second, third, fourth, and fifth sides of the fin active region. A gate electrode layer is formed over the gate insulation layer to substantially surround the first, second, third, fourth, and fifth sides of the fin active region. The first, third, and fifth sides have substantially different slopes. The third and fourth sides are curved surfaces.
1. A method for fabricating a semiconductor device, the method comprising:
forming a first fin active region on a substrate having a recessed active region, the first fin active region extending above the recessed active region;
forming a device isolation layer in the semiconductor substrate on opposite sides of the recessed active region, wherein a width of the recessed active region between the device isolation layers is greater than a width of the first fin active region;
shaping the first fin active region to a second fin active region having first, second, third, fourth, and fifth sides;
forming a gate insulation layer over the second fin active region; and
forming a gate electrode layer over the gate insulation layer to substantially surround the first, second, third, fourth, and fifth sides of the second fin active region.
2. The method of claim 1 , wherein the forming of the first fin active region comprises:
etching the substrate to define the first fin active region and the recessed active region on the substrate; and
etching each device isolation layer to a predetermined thickness, wherein each etched device isolation layer is substantially flushed to the recessed active region.
3. The method of claim 2 , wherein each device isolation layer is etched by using a wet etching process.
4. The method of claim 1 , wherein the first fin active region defines three channels, and the second fin active region defines five channels.
5. The method of claim 4 , wherein the shaping process comprises:
etching sidewalls and an upper side of the first fin active region by performing an etch-back process.
6. The method of claim 5 , wherein the upper side and the sidewalls of the first fin active region are etched to a thickness ranging from approximately 10 Å to approximately 500 Å.
7. The method of claim 1 , wherein the gate electrode layer is formed to a thickness approximately 100 Å or more.
8. The method of claim 1 , wherein the forming of the gate electrode layer comprises:
forming a gate electrode layer with a thickness greater than the second fin active region by at least 500 Å; and
planarizing the gate electrode layer by performing a chemical mechanical polishing (CMP) process.
9. The method of claim 8 , further comprising:
patterning the planarized gate electrode layer to define a gate electrode that substantially surrounds the first, second, third, fourth, and fifth sides of the second fin active region.
10. The method of claim 9 , wherein a first mask used to pattern the gate electrode layer has substantially the same pattern as a second mask used to form the first fin active region.
11. The method of claim 10 , wherein a line width of the first mask ranges from approximately 10 nm to approximately 100 nm.
12. The method of claim 1 , wherein the first, third, and fifth sides have substantially different slopes.
13. The method of claim 12 , wherein the third and fourth sides are curved surfaces.