Method for manufacturing a transistor of a semiconductor memory device
View Patent ↗A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
1. A method for manufacturing a transistor of a semiconductor memory device, comprising:
forming a hard mask layer pattern on a semiconductor substrate over a plurality of active regions;
forming a plurality of device isolation trenches in a device isolation region of the semiconductor substrate by using the hard mask layer pattern as an etching mask;
forming a trench device isolation layer by filling up the device isolation trenches with an insulation layer;
etching a part of the trench device isolation layer by a predetermined depth by use of a first mask layer pattern, to form a plurality of first and second trench device isolation layers arranged alternately with each other, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height;
removing the hard mask layer pattern;
etching the active regions by a predetermined depth by use of a second mask layer pattern, to form a recess region in each of the active regions, the recess region having a stepped profile at a boundary portion thereof and a height higher than that of the second trench device isolation layers to form an upwardly protruded portion between two adjacent second trench device isolation layers; and
forming a plurality gate insulation layers and plurality of gate stacks on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
2. The method of claim 1 , wherein the hard mask layer pattern includes a pad oxide layer pattern having a thickness of about 100 Å to about 200 Å, and a pad nitride layer pattern having a thickness of about 500 Å to about 800 Å, which are laminated in this sequence.
3. The method of claim 1 , comprising forming the device isolation trenches to have a depth of about 2000 Å to about 4000 Å.
4. The method of claim 1 , comprising etching the trench device isolation layer using the first mask layer pattern to remove about two thirds of the entire thickness of the trench device isolation layer.
5. The method of claim 1 , comprising etching the each active region using the second mask layer pattern such that the resulting recess region has a depth equal to about one third of the first thickness of the first trench device isolation layers.
6. The method of claim 1 , comprising forming the gate stacks by the first mask layer pattern.
7. The method of claim 1 , wherein each of the gate stacks includes a doped polysilicon layer having a thickness of about 400 Å to about 700 Å, and a tungsten-silicide layer having a thickness of about 1000 Å to about 1500 Å.
8. A transistor of a semiconductor memory device, comprising:
a semiconductor substrate having a plurality of active regions and a device isolation region;
a plurality of first and second trench device isolation layers arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness, and the second trench device isolation layers having a second thickness smaller than the first thickness;
a recess region having a predetermined depth formed in each of the active regions, the recess region having a stepped profile and an upwardly protruded portion between two adjacent second trench device isolation layers;
a plurality of gate insulation layers and gate stacks; and
at least one of the gate stacks formed on one of the gate insulation layers and having a stripe form crossing one of the active regions to partially fill the recess region,
wherein the transistor has a fin field effect transistor structure, and
wherein each active region of the plurality of active regions has a central region and opposite edge regions, a height of an upper surface of the central region being lower than a height of an upper surface of the opposite edge regions.
9. The transistor of claim 8, wherein the first thickness of the first trench device isolation layers is in a range from about 2000 Å to about 4000 Å.
10. The transistor of claim 9, wherein the second thickness of the second trench device isolation layers is about one third of the first thickness of the first trench device isolation layers.
11. The transistor of claim 8, wherein the thickness of the protruded portion of the recess region is substantially equal to the second thickness of the second trench device isolation layers.
12. The transistor of claim 8, wherein each of the gate stacks has a stripe form, and is formed to overlap with the second trench device isolation layers.
13. The transistor of claim 8, wherein the plurality of gate insulation layers and gate stacks overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.
14. The transistor of claim 8, wherein each of the gate stacks includes a doped polysilicon layer having a thickness of about 400 Å to about 700 Å.
15. The transistor of claim 14, wherein each of the gate stacks includes a tungsten-silicide layer having a thickness of about 1000 Å to about 1500 Å.
16. The transistor of claim 8, wherein the plurality of gate insulation layers and the plurality of gate stacks are formed at least in part in the recess region.