Duty cycle correction circuit for use in a semiconductor device
View Patent ↗A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.
1. A duty cycle correction circuit for use in a semiconductor device, the circuit comprising:
a modulator having at least one or more transistors, the modulator for receiving a control signal through a source terminal and a bulk of one of the transistors and for correcting a duty cycle in response to an external clock signal;
a driver for converting an output signal of the modulator into a full swing level and for outputting the converted output signal of the modulator; and
a feedback loop circuit for generating the control signal in response to an output signal of the driver.
2. The circuit of claim 1 , wherein the feedback loop circuit comprises:
a detector for integrating an output signal of the driver;
a comparator for comparing an output signal of the detector with a ref rence signal and for outputting a comparison result; and
a stabilizer for stabilizing an output signal of the comparator and for outputting the control signal.
3. The circuit of claim 2 , wherein the modulator is an inverter circuit in which the transistors include one PMOS transistor and one NMOS transistor connected in series and which receive the external clock signal through a common gate.
4. The circuit of claim 3 , wherein the detector has a low pass filter.
5. The circuit of claim 4 , wherein the comparator includes an error amplifier.
6. The circuit of claim 5 , wherein the stabilizer includes a low pass filter.
7. The circuit of claim 6 , wherein a source of the NMOS transistor is connected to a ground terminal and the control signal is applied to a source and a bulk of the PMOS transistor.
8. The circuit of claim 6 , wherein he PMOS transistor receives an applied power source voltage through its source and the control signal is applied to a source and a bulk of the NMOS transistor.
9. The circuit of claim 3 , wherein the driver includes a buffer.
10. A method for correcting a duty cycle of a semiconductor device synchronized with an external clock signal, the method comprising:
(a) receiving, at a source and a bulk of one of a plurality of transistors of a modulator, a control signal;
(b) correcting, at the modulator, a duty cycle in response to the external clock signal;
(c) converting, at a driver, an output signal of the modulator into a fill swing level;
(d) outputting, at the driver, the converted output signal of the modulator; and
(e) generating, at a feedback loop circuit, the control signal in response to an output signal of the driver.
11. The method of claim 10 , wherein the step (e), comprises;
(e-1) integrating, at a detector, an output signal of the driver;
(e-2) comparing, at a comparator, an output signal of the detector with a reference signal;
(e-3) outputting, from the comparator, a comparison result;
(e-4) stabilizing, at a stabilizer, an output signal of the comparator; and
(e-5) outputting, at the stabilizer, the control signal.
12. The method of claim 10 , further comprising:
repeating steps (a–e) until a desired duty cycle is obtained.
13. The method of claim 12 , wherein the desired duty cycle is 50%.
14. A duty cycle correction circuit for use in a semiconductor device, the circuit comprising:
a modulator having at least one or more transistors, the modulator for receiving a control signal through a source terminal and a bulk of one of the transistors arid for correcting a duty cycle in response to an external clock signal;
a driver for converting an output signal of the modulator into a full swing level and for outputting the converted output signal of the modulator; and
a feedback loop circuit for generating the control signal in response to an output signal of the driver;
wherein the transistors include one PMOS transistor and one NMOS transistor connected in series and which receive the external clock signal through a common gate;
wherein a source of the NMOS transistor is connected to a ground terminal and the control signal is applied to a source and a bulk of the PMOS transistor.
15. A duty cycle correction circuit for use in a semiconductor device, the circuit comprising:
a modulator having at least one or more transistors, the modulator for receiving a control signal through a source terminal and a bulk of one of the transistors and for correcting a duty cycle in response to an external clock signal;
a driver for converting an output signal of the modulator into a full swing level and for outputting the converted output signal of the modulator; and
a feedback loop circuit for generating the control signal in response to an output signal of the driver;
wherein the transistors include one PMOS transistor and one NMOS transistor connected in series and which receive the external clock signal through a common gate;
wherein the PMOS transistor receives a power source voltage through its source and the control signal is applied to a source and a bulk of the NMOS transistor.