Granted Patent B2

US 6,884,673 · App. 10/160,646 · Granted Apr 26, 2005

Abstract

Claims (56)

1. A method of forming an integrated circuit device, comprising:

providing a substrate;

forming an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate;

forming a lower mold layer and an upper mold layer sequentially on the interlevel-insulating layer that have an opening therein that is wider than the hole;

forming a unitary lower electrode of a capacitor that is disposed on the substrate and is received through the opening in the upper and lower mold layers and has contact plug portion thereof that is disposed in the hole;

removing the upper mold layer;

forming a dielectric layer on the lower electrode of the capacitor; and

forming an upper electrode of the capacitor on the dielectric layer.

2. The method of claim 1 , further comprising:

forming a barrier layer between the contact plug portion of the lower electrode of the capacitor and both the substrate and sidewalls of the interlevel-insulating layer.

3. The method of claim 1 , further comprising:

forming an etch stop layer on the lower mold layer that has an opening therein through which the lower electrode of the capacitor is received.

4. The method of claim 1 , wherein the upper an lower electrodes of the capacitor comprise Pt, Ru, and/or Ir.

5. The method of claim 1 , wherein forming the lower mold layer and the upper mold layer comprises:

filling the hole with a sacrificial layer;

forming the lower mold layer, an etch stop layer, and an upper mold layer sequentially on the sacrificial layer and the interlevel insulating layer;

patterning the upper mold layer, the etch stop layer, and the lower mold layer to form an opening exposing an upper surface of the sacrificial layer; and

removing the sacrificial layer from the hole.

6. The method of claim 1 , wherein removing the upper mold layer comprises:

removing the upper mold layer using wet etching.

7. The method of claim 1 , wherein the lower electrode of the capacitor has a cylindrical shape that partially fills the opening along sidewalls of the upper and lower mold layers.

8. A method of forming an integrated circuit device, comprising:

providing a substrate;

forming an interlevel-insulating layer on the substrate that has a hole therein that exposes the substrate;

forming a contact plug in the hole on the barrier layer;

forming a lower mold layer and an upper mold layer sequentially on the interlevel-insulating layer that have an opening therein that is wider than the hole;

forming a lower electrode of a capacitor that is disposed on the contact plug and engages the contact plug at a boundary therebetween, the lover electrode being received through the opening in the lower and the upper mold layers;

removing the upper mold layer;

forming a dielectric layer on the lower electrode of the capacitor; and

forming an upper electrode of the capacitor on the dielectric layer.

9. The method of claim 8 , further comprising:

forming an etch stop layer on the lower mold layer that has an opening therein through which the lower electrode of the capacitor is received.

10. The method of claim 8 , wherein the upper and lower electrodes of the capacitor comprise Pt, Ru, and/or Ir.

11. The method of claim 8 , further comprising:

forming a barrier layer on the exposed portion of the substrate and on sidewalls of the interlevel-insulating layer.

12. The method of claim 8 , wherein removing the upper mold layer comprises:

removing the upper mold layer using wet etching.

13. The method of claim 8 , wherein the lower electrode of the capacitor has a cylindrical shape that partially fills the opening along sidewalls of the upper and the lower mold layers.

14. A method of forming an integrated circuit device, comprising:

providing a substrate;

forming an interlevel-insulating layer on the substrate;

patterning the interlevel-insulating layer to form a contact hole that exposes the substrate;

forming a barrier layer on the interlevel-insulating layer including sidewalls of the interlayer insulating layer that define the contact hole and on an exposed portion of the substrate;

forming a first sacrificial layer on the barrier layer;

etching the first sacrificial layer and the barrier layer so as to expose the interlayer-insulating layer;

forming a mold layer on the interlevel-insulating layer and the first sacrificial layer in the contact hole;

patterning the mold layer to form an opening that exposes the first sacrificial layer in the contact hole;

etching the first sacrificial layer so as to expose the barrier layer in the contact hole;

forming a lower electrode of a capacitor in the opening that has a contact plug portion that is disposed in the contact hole, the lower electrode having a cylindrical shape that partially fills the opening along sidewalls of the mold layer;

forming a second sacrificial layer in the opening on the lower electrode;

etching the second sacrificial layer using the mold layer as an etch stop layer;

etching at least a portion of the mold layer;

forming a dielectric layer on the lower electrode of the capacitor and on the interlevel-insulating layer; and

forming an upper electrode of the capacitor on the dielectric layer.

15. The method of claim 14 , wherein etching at least the portion of the mold layer comprises:

etching the second sacrificial layer so as to expose sidewalls and a bottom surface of the lower electrode.

Assignments (10)