Granted Patent B2

US 7,088,152 · App. 10/848,913 · Granted Aug 8, 2006

Abstract

Claims (109)

1. A semiconductor memory device including a data driving circuit, comprising:

a driver in which a driving current is controlled in response to predetermined bits of digital control signal and which receives a differential input data signal to generate a differential output data signal; and

a digital control signal generator for storing and generating the digital control signal,

wherein the driver includes:

a pre-driver for passing a pre driving current in response to a bias voltage and for receiving the differential input data signal to generate first and second signals; and

a main driver in which a main driving current is controlled in response to the digital control signal and which generates the differential output data signal in response to the first and second signals.

2. The circuit of claim 1 , wherein the pre-driver includes:

a first pre driving circuit having a first load connected between a power voltage and a first node, a first switching transistor for being connected to the first node and for being switched in response to an input data signal of the differential input data signals, and a first pre driving current source connected between the first switching transistor and a ground voltage and passing the pre driving current in response to the bias voltage, wherein the first pre driving circuit generates the first signal through the first node; and

a second pre driving circuit having a second load connected between the power voltage and the node, a second switching transistor for being connected to the second node and for being switched in response to an inverted input data signal of the differential input data signal, and a second pre driving current source connected between the second switching transistor and the ground voltage and passing the pre driving current in response to the bias voltage, wherein the second pre driving circuit generates the second signal through the second node.

3. The circuit of claim 1 , wherein the main driver includes:

a third load connected between the power voltage and a third node;

a fourth load connected between the power voltage and a fourth node;

a first transistor connected between the third node and a fifth node and having a gate receiving the first signal;

a second transistor connected between the fourth node and the fifth node and having a gate receiving the second signal; and

a main driving current source connected in parallel between the fifth node and the ground voltage and which a main driving current is controlled in response to the digital control signal,

wherein an non-inverted data signal of the differential output data signals is generated through the third node and an inverted output data signal of the differential output data signals is generated through the fourth node.

4. The circuit of claim 3 , wherein the main driving current source includes:

a third transistor having a gate receiving the bias voltage; and

a predetermined number of fourth transistors having gates receiving respective bit signals of the digital control signal and connected in parallel to the third transistor.

5. The circuit of claim 3 , wherein the predetermined number of fourth transistors differ in channel width respectively.

6. The circuit of claim 1 :

in the pre-driver, the pre driving current is controlled in response to one part of predetermined bits of the digital control signal and receives the differential input data signals to generate the first and second signals; and

in the main driver, the main driving current is controlled in response to another part of the predetermined bits of the digital control signal and generates the differential output data signal in response to the first and second signals.

7. The circuit of claim 6 , wherein the pre-driver includes:

a first pre driving circuit having a first load connected between a power voltage and a first node, a first switching transistor for being connected to the first node and for being switched in response to an input data signal of the differential input data signals, and a first pre driving current source which is connected between the first switching transistor and a ground voltage and which the pre driving current is controlled in response to part of bit of the digital control signal, wherein the first pre driving circuit generates the first signal through the first node; and

a second pre driving circuit having a second load connected between the power voltage and a second node, a second switching transistor for being connected to the second node and for being switched in response to an inverted input data signal of the differential input data signals, and a second pre driving current source which is connected between the second switching transistor and the ground voltage and which the pre driving current is controlled in response to other part of bit of the digital control signal, wherein the second pre driving circuit generates the second signal through the second node.

8. The circuit of claim 7 , wherein the first pre driving circuit includes:

a first transistor having a gate receiving the bias voltage; and

a predetermined number of second transistors having gates receiving respective bit signals of one part of predetermined bits of the digital control signal and connected in parallel to the first transistor.

9. The circuit of claim 8 , wherein the predetermined number of second transistors differ in channel width respectively.

10. The circuit of claim 7 , wherein the second driving circuit includes:

a third transistor having a gate receiving the bias voltage; and

a predetermined number of fourth transistors having gates receiving respective bit signals of part of bits of the digital control signal and connected in parallel to the third transistor.

11. The circuit of claim 10 , wherein the predetermined number of fourth transistors differ in channel width respectively.

12. The circuit of claim 6 , wherein the main driver includes:

a third load connected between the power voltage and a third node;

a fourth load connected between the power voltage and a fourth node;

a first transistor connected between the third node and a fifth node and having a gate receiving the first signal;

a second transistor connected between the fourth node and the fifth node and having a gate receiving the second signal; and

a main driving current source connected in parallel between the fifth node and the ground voltage and controlling a main driving current in response to other bit of the predetermined bit of the second digital control signal,

wherein an non-inverted data signal of the differential output data signals is generated through the third node and an inverted output data signal of the differential output data signals is generated through the fourth node.

13. The circuit of claim 12 , wherein the main driving current source includes:

a fifth transistor having a gate receiving the bias voltage; and

a predetermined number of sixth transistors having gates receiving respective bit signals of other bit of the digital control signal and connected in parallel to the fifth transistor.

14. The circuit of claim 13 , wherein the predetermined number of sixth transistors differ in channel width respectively.

15. A data driving circuit, comprising:

a bias current generating circuit for generating a bias current in response to predetermined bits of digital control signal; and

a driver for mirroring the bias current to generate a driving current and receiving a differential input data signal to generate differential output data signals;

wherein the driver includes:

a pre-driver for mirroring the bias current to pass a pre driving current and for receiving the differential input data signals to generate first and second signals; and

a main driver for mirroring the bias current to pass a main driving current and receiving the first and second signals to generate the differential output data signals.

16. The circuit of claim 15 , wherein the bias current generating circuit includes:

a digital control signal generating circuit for storing and generating the digital control signal;

a first load connected between a power voltage and a first node;

a predetermined number of first transistors connected between the first node and a second node, respectively having gates receiving the predetermined bit of digital control signal and generating the bias current;

a comparator comparing a voltage of the first node to a predetermined voltage to generate an output voltage to the second node; and

a second transistor connected between the second node and a ground voltage, having a gate connected to the second node and passing the bias current.

17. A data driving circuit, comprising:

a bias current generating circuit for generating a bias current in response to predetermined bits of digital control signals; and

a driver for mirroring the bias current to generate a driving current and receiving a differential input data signal to generate differential output data signals;

wherein the driver includes:

a pre-driver for passing a pre driving current in response to a bias voltage and for receiving the differential input data signals to generate first and second signals; and

a main driver for mirroring the bias current to pass a main driving current and receiving the first and second signals to generate the differential output data signals.

18. The circuit of claim 17 , wherein the bias current generating circuit includes:

a digital control signal generating circuit for storing and generating the digital control signal;

a first load connected between a power voltage and a first node;

a predetermined number of first transistors connected between the first node and a second node, respectively having gates receiving the predetermined bit of digital control signal and generating the bias current;

a comparator comparing a voltage of the first node to a predetermined voltage to generate an output voltage to the second node; and

a second transistor connected between the second node and a ground voltage, having a gate connected to the second node and passing the bias current.

19. A semiconductor device having a plurality of data driving circuits, comprising:

each of the plurality of the data driving circuit includes

a driver in which a driving current is controlled in response to predetermined bits of digital control signal and which receives a differential input data signal to generate a differential output data signals; and

a digital control signal generator for storing and generating the digital control signal;

wherein the driver includes:

a pre-driver for passing a pre driving current in response to a bias voltage and for receiving the differential input data signals to generate first and second signals; and

a main driver in which a main driving current is controlled in response to the digital control signal and which generates the differential output data signals in response to the first and second signals.

20. A semiconductor device having a plurality of data driving circuits, comprising:

each of the plurality of the data driving circuit includes

a driver in which a driving current is controlled in response to predetermined bits of digital control signal and which receives a differential input data signal to generate a differential output data signals; and

a digital control signal generator for storing and generating the digital control signal,

wherein the driver includes:

a pre-driver in which a pre driving current is controlled in response to one part of predetermined bits of the digital control signal and which receives the differential input data signals to generate first and second signals; and

a main driver in which a main driving current is controlled in response to other part of predetermined bits of the digital control signal and which generates the differential output data signals in response to the first and second signals.

21. A semiconductor device having a plurality of data driving circuits, comprising:

each of the plurality of the data driving circuit includes:

a bias current generating circuit for generating a bias current in response to predetermined bits of digital control signal; and

a driver for mirroring the bias current to generate a driving current and receiving a differential input data signal to generate differential output data signals,

wherein the driver includes:

a pre-driver for mirroring the bias current to pass a pre driving current and for receiving the differential input data signal to generate first and second signals; and

a main driver for mirroring the bias current to pass a main driving current and receiving the first and second signals to generate the differential output data signals.

22. The circuit of claim 21 , wherein the bias current generating circuit includes:

a digital control signal generating circuit for storing and generating the digital control signal;

a first load connected between a power voltage and a first node;

a predetermined number of first transistors connected between the first node and a second node, respectively having gates receiving respective bit signals of the digital control signal and generating the bias current;

a comparator comparing a voltage of the first node and a predetermined voltage to generate an output voltage to the second node; and

a second transistor connected between the second node and a ground voltage, having a gate connected to the second node and passing the bias current.

23. A semiconductor device having a plurality of data driving circuit, comprising:

each of the plurality of the data driving circuit includes:

a bias current generating circuit for generating a bias current in response to predetermined bits of digital control signal; and

a driver for mirroring the bias current to generate a driving current and receiving a differential input data signal to generate differential output data signal,

wherein the driver includes:

a pre-driver for mirroring the bias current to pass a pre driving current and for receiving the differential input data signal to generate first and second signals; and

a main driver for mirroring the bias current to pass a main driving current and receiving the first and second signals to generate the differential output data signals.

24. The circuit of claim 23 , wherein the bias current generating circuit includes;

a digital control signal generating circuit for storing and generating the digital control signal;

a first load connected between a power voltage and a first node;

a predetermined number of first transistors connected between the first node and a second node, respectively having gates receiving respective bit signals of the digital control signal and generating the bias current;

a comparator comparing a voltage of the first node and a predetermined voltage to generate an output voltage to the second node; and

a second transistor connected between the second node and a round voltage, having a gate connected to the second node and passing the bias current.

Assignments (10)