Granted Patent E1

US 44,532 · App. 13/586,272 · Granted Oct 8, 2013

Abstract

Claims (36)

1. A method for manufacturing a transistor of a semiconductor memory device, comprising:

forming a hard mask layer pattern on a semiconductor substrate over a plurality of active regions;

forming a plurality of device isolation trenches in a device isolation region of the semiconductor substrate by using the hard mask layer pattern as an etching mask;

forming a trench device isolation layer by filling up the device isolation trenches with an insulation layer;

etching a part of the trench device isolation layer by a predetermined depth by use of a first mask layer pattern, to form a plurality of first and second trench device isolation layers arranged alternately with each other, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height;

removing the hard mask layer pattern;

etching the active regions by a predetermined depth by use of a second mask layer pattern, to form a recess region in each of the active regions, the recess region having a stepped profile at a boundary portion thereof and a height higher than that of the second trench device isolation layers to form an upwardly protruded portion between two adjacent second trench device isolation layers; and

forming a plurality of gate insulation layers and a plurality of gate stacks on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.

2. The method of claim 1 , wherein the hard mask layer pattern includes a pad oxide layer pattern having a thickness of about 100 Å to about 200 Å, and a pad nitride layer pattern having a thickness of about 500 Å to about 800 Å, which are laminated in this sequence.

3. The method of claim 1 , comprising forming the device isolation trenches to have a depth of about 2000 Å to about 4000 Å.

4. The method of claim 1 , comprising etching the trench device isolation layer using the first mask layer pattern to remove about two thirds of the entire thickness of the trench device isolation layer.

5. The method of claim 1 , comprising etching the each active region using the second mask layer pattern such that the resulting recess region has a depth equal to about one third of the first thickness of the first trench device isolation layers.

6. The method of claim 1 , comprising forming the gate stacks by the first mask layer pattern.

7. The method of claim 1 , wherein each of the gate stacks includes a doped polysilicon layer having a thickness of about 400 Å to about 700 Å, and a tungsten-silicide layer having a thickness of about 1000 Å to about 1500 Å.

8. A method for manufacturing a transistor of a semiconductor memory device, comprising:

forming a hard mask layer pattern on a semiconductor substrate over a plurality of active regions;

forming a plurality of device isolation trenches in a device isolation region of the semiconductor substrate by using the hard mask layer pattern as an etching mask;

forming a trench device isolation layer by filling up the device isolation trenches with an insulation layer;

etching a part of the trench device isolation layer by a predetermined depth, to form a plurality of first and second trench device isolation layers arranged alternately with each other, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height;

etching the active regions by a predetermined depth, to form a recess region in each of the active regions, the recess region having a stepped profile at a boundary portion thereof and a height higher than that of the second trench device isolation layers to form an upwardly protruded portion between two adjacent second trench device isolation layers; and

forming a plurality of gate insulation layers and a plurality of gate stacks on the gate insulation layer.

9. The method of claim 8, further comprising removing the hard mask layer pattern after forming the trench device isolation layer.

10. The method of claim 8, wherein the plurality of gate insulation layers and the plurality of gate stacks are formed to overlap with the stepped profile of the respective active regions.

11. The method of claim 8, wherein the plurality of gate insulation layers and the plurality of gate stacks are formed to overlap with the protruded portion of the relevant recess region.

12. The method of claim 8, wherein the plurality of gate insulation layers and the plurality of gate stacks are formed at least in part in the recess region.

13. The method of claim 8, wherein:

etching the part of the trench device isolation layer comprises using a first mask layer pattern; and

etching the active regions comprises using a second mask layer pattern.

14. The method of claim 8, comprising forming the device isolation trenches to have a depth of about 2000 Å to about 4000 Å.

15. The method of claim 8, comprising etching the trench device isolation layer to remove about two thirds of the entire thickness of the trench device isolation layer.

16. The method of claim 8, comprising etching each active region such that the resulting recess region has a depth equal to about one third of the first thickness of the first trench device isolation layers.

17. The method of claim 8, wherein:

etching a part of the trench device isolation layer comprises using a first mask layer pattern,

the method further comprising:

forming the gate stacks by the first mask layer pattern.

18. The method of claim 8, wherein each of the gate stacks includes a doped polysilicon layer having a thickness of about 400 Å to about 700 Å.

Assignments (8)