Method of manufacturing semiconductor device with recess and Fin structure
View Patent ↗The semiconductor device includes an active region, a recess, a Fin channel region, a gate insulating film, and a gate electrode. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess is formed by etching the active region and its neighboring device isolation structure using an island shaped recess gate mask as an etching mask. The Fin channel region is formed on the semiconductor substrate at a lower part of the recess. The gate insulating film is formed over the active region including the Fin channel region and the recess. The gate electrode is formed over the gate insulating film to fill up the Fin channel region and the recess.
1. A method for manufacturing a semiconductor device, the method comprising:
forming an active region on a semiconductor substrate, the active region being elongated in a first direction;
forming a recess in a channel region of the active region so that a width in the first direction of a lower part of the recess is greater than that of an upper part of the recess;
forming a device isolation structure defining the active region, wherein forming the device isolation structure comprises:
etching opposing portions extending in a second direction, which is substantially orthogonal to the first direction, from the lower part of the recess, each etched portion having a depth lower than an upper surface of the active region,
wherein the lower part of the recess has a width in the second direction that is greater than a width of the upper part of the recess in the second direction, and
wherein a minimum width of the upper part of the recess in the second direction is greater than a maximum width of the active region in the recess;
forming a gate insulating film over portions of the active region in the recess; and
forming a gate electrode over portions of the gate insulating film and filling the recess and the etched portions.
2. The method according to claim 1 , wherein the etching opposing portions further comprises etching opposing portions to have a depth lower than the upper surface of the active region such that the active region at the bottom of the recess protrudes in an upward fin shape into the recess.
3. The method according to claim 1 , wherein forming the recess further comprises:
forming an upper part with a vertical profile having a first width in the first direction; and
forming a lower part with a curved profile adjacent and immediately below the first part having a second width in the first direction larger than the first width.
4. The method according to claim 3 , wherein the curved profile in the first direction of the lower part of the recess is elliptical or circular.
5. The method according to claim 3 , wherein the etching the opposing portions further comprises etching the opposing portions to have a depth lower than the upper surface of the active region such that the active region at the bottom of the lower part of the recess protrudes in an upward fin shape into the lower part of the recess.
6. The method according to claim 1 , wherein forming the recess further comprises etching the recess such that a minimum width of the recess in the second direction is greater than a maximum width in the second direction of the gate insulating film over active region.
7. The method according to claim 1 , wherein forming the device isolation structure further comprises forming a stacked structure of a first liner oxide film, a liner nitride film and a filling oxide film.
8. The method according to claim 1 , wherein forming the device isolation structure further comprises forming a stacked structure of a first and second oxide films, each having an etching rate different from the other.
9. The method according to claim 1 , wherein forming the recess further comprises forming the recess such that the width of the upper part of the recess in the second direction is greater than the maximum width of the active region in recess by a distance 2 E, where 0<E<½ F, and a distance F is the distance between neighboring gate regions in the first direction.
10. The method according to claim 1 , wherein the gate insulating film is selected from the group consisting of an oxide film, a nitride film, and combination thereof.
11. The method according to claim 1 , wherein the gate electrode is selected from the group consisting of a polysilicon film, a titanium nitride film, a tungsten film, and combinations thereof.