High voltage generator circuit with ripple stabilization function
View Patent ↗The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage. After the high voltage reaches the target voltage, the high voltage cyclically falls below the target voltage. After the high voltage reaches the target voltage, a pump clock generator block circuit limits the transmission of the pump clock signal so that only N clock signals are gate to the charge pump each cycle, where N is the number one or greater.
1. A high voltage generator circuit comprising:
a charge pump for generating a high voltage;
an oscillator for generating pump clock signal pulses for driving the charge pump when the high voltage is below a target voltage, the high voltage initially reaching a target voltage and thereafter the high voltage falls below the target voltage cyclically, once in a cycle; and
a pump clock generator block circuit for limiting the transmission of the pump clock signal pulses to the charge pump to only N pump clock signal pulses per the cycle, where N is a predetermined integer.
2. The high voltage generator circuit of claim 1 , wherein after the high voltage reaches the target voltage, the pump clock generator block circuit limits the transmission of the pump clock signal pulses to the charge pump to only one pump clock signal pulses per cycle.
3. The high voltage generator circuit of claim 2 , wherein when the high voltage has not initially reached the target voltage, the transmission of the pump clock signal pulses is not limited.
4. The high voltage generator circuit of claim 1 , wherein the pump clock generator block circuit limits the transmission of the pump clock signal pulses so that only one pump clock signal pulse is outputted to the charge pump when the high voltage is lower than the target voltage.
5. The high voltage generator circuit of claim 1 , wherein the pump clock generator block circuit is structured so that the transmission limitation of the pump clock signal pulses is programmable.
6. A high voltage generator circuit comprising:
a charge pump for generating a high voltage in response to receiving pump clock pulses;
a clock enable signal generator for generating a clock enable signal according to whether the high voltage is lower than a reference voltage;
a clock driver for outputting oscillation signal pulses as clock pulses in response to the clock enable signal; and
a ripple stabilizer including a counter that counts the oscillation signal pulses, the ripple stabilizer for outputting a limited number of the clock pulses to the charge pump, the limited number of the clock pulses being the pump clock pulses, after the counter counts a predetermined number of the oscillation signal pulses.
7. The high voltage generator circuit of claim 6 , wherein after the high voltage reaches the target voltage, the ripple stabilizer limits the number of clock pulses to only one.
8. The high voltage generator circuit of claim 7 , wherein until the high voltage reaches the target voltage, the number of clock pulses is not limited.
9. The high voltage generator circuit of claim 6 , wherein the ripple stabilizer is structured so that the limit on the number of clock pulses is programmable.
10. The high voltage generator circuit of claim 6 , wherein the ripple stabilizer limits the number of clock pulses when the high voltage is lower than the target voltage.
11. The high voltage generator circuit of claim 6 , wherein the ripple stabilizer includes:
a clock limit signal generating section for generating a clock limit signal synchronized with the oscillation signal pulses according to whether the high voltage reaches the target voltage; and
a switch for selectively outputting the clock pulses as the pump clock pulses in response to the clock limit signal.
12. The high voltage generator circuit of claim 11 , wherein the ripple stabilizer further includes a limit period computing section for generating a limit end signal in response to the clock limit signal, and
wherein the clock limit signal is inactivated when the limit end signal is activated.
13. The high voltage generator circuit of claim 12 , wherein when the clock limit signal is inactivated, the switch outputs the clock pulses as the pump clock pulses without limitation.
14. The high voltage generator circuit of claim 13 , wherein the limit end signal is activated after the clock limit signal is activated and a predetermined time passes.
15. The high voltage generator circuit of claim 12 , wherein when the clock limit signal is activated, the switch limits the clock pulses to be cyclically outputted as much as a first clock cycle.
16. The high voltage generator circuit of claim 11 , wherein the switch is structured to output the clock pulses as the pump clock pulses irrespective of the clock limit signal according to a signal indicating whether a clock limit function is in use.
17. A method for generating a high voltage, the method comprising:
generating a pump clock signal, comprising pulses, according to whether the high voltage reaches a target voltage; and
generating the high voltage in response to the pump clock signal;
after the high voltage reaches the target voltage, limiting the pump clock signal to be cyclically generated, so there are a limited number of pulses per cycle.
18. The method of claim 17 , wherein when the high voltage has not reached the target voltage, the pump clock signal is not limited.
19. The method of claim 17 , wherein the pump clock pulses are outputted only during a first clock cycle whenever the high voltage is lower than the target voltage.
20. A high voltage generator circuit comprising:
an oscillator to generate a pump clock signal comprising a plurality of pulses;
a charge pump for generating a high voltage upon receiving the pulses;
a comparator circuit to determine if the charge pump is generating a target high voltage;
a counter circuit to determine a limit period after the comparator circuit has determined that the charge pump is generating a voltage at or above the target high voltage; and
a pump clock generator block circuit to prevent the charge pump from receiving the pulses during the limit period, and to transmit an N number of the pulses to the charge pump at the end of each limit period.
21. The high voltage generator circuit of claim 20 , wherein the charge pump generates the voltage equal to the target high voltage once per the limit period.
22. The high voltage generator circuit of claim 20 , wherein the counter circuit is programmable so that the limit period is changeable.
23. The high voltage generator circuit of claim 20 , wherein the voltage is cyclic with a period equal to the limit period.
24. A high voltage generator circuit comprising:
a charge pump for generating a high voltage in response to a pump clock signal;
a ripple stabilizer having a first mode of operation in which the charge pump is supplied with the pump clock signal and a second mode of operation in which the charge pump is prevented from receiving the pump clock signal;
a clock driver to supply the ripple stabilizer with the pump clock signal in response to a clock enable signal; and
a comparator to generate the clock enable signal according to whether the high voltage is lower than a target voltage,
wherein the ripple stabilizer includes
a switch circuit to output the pump clock signal in response to a clock limit signal in the first mode,
a clock limit signal generating circuit to generate the clock limit signal using a latch circuit, and
a counter that is reset by the clock limit signal, the counter to determine a time period for which the switch circuit outputs the pump clock signal in the first mode, wherein the latch circuit is responsive to the counter.