Granted Patent B2

US 7,410,866 · App. 11/204,660 · Granted Aug 12, 2008

Abstract

Claims (23)

1. A method for forming a semiconductor device, the method comprising:

forming an inter-layer insulation layer over a substrate, wherein the inter-layer insulation layer comprises a first oxide-based layer;

etching the inter-layer insulation layer to form a plurality of first contact holes;

forming a first insulation layer on sidewalls of the first contact holes, the first insulation layer including a plurality of spacers and the spacers formed by using a material having a first etch rate, wherein the first insulation layer comprises a second oxide-based layer;

forming a plurality of storage-node contact plugs that are filled into the first contact holes;

forming a second insulation layer over the storage-node contact plugs, the second insulation layer formed by using a nitride-based material having a second etch rate that is different from the first etch rate;

forming a third insulation layer over the second insulation layer, wherein the third insulation layer comprises a third oxide-based layer;

etching the third insulation layer using the second insulation layer as an etch stop layer;

etching the second insulation layer to form a plurality of second contact holes, wherein the second contact holes expose the storage node contact plugs; and

forming a storage node on each of the second contact holes.

2. The method of claim 1 , wherein the second oxide-based layer is one selected from a group consisting of an aluminum oxide (Al 2 O 3 ) layer, a plasma enhanced tetraethylorthosilicate (PE-TEOS) oxide layer, an atomic layer deposition (ALD) oxide layer, and a tantalum oxide (Ta 2 O 5 ) layer.

3. The method of claim 2 , wherein the first insulation layer has a thickness ranging from approximately 50 Å to approximately 500 Å.

4. The method of claim 1 , wherein the second insulation layer is one selected from a group consisting of a plasma enhanced chemical vapor deposition (PE-CVD) nitride layer, an ALD nitride layer, and a low-pressure (LP) nitride layer.

5. The method of claim 4 , wherein the second insulation layer has a thickness ranging from approximately 100 Å to approximately 1,000 Å.

6. The method of claim 1 , wherein the third oxide-based layer is formed of one of a single layer of the same material for forming the first oxide-based layer and stacked layers thereof.

7. The method of claim 1 , wherein the third oxide-based layer is formed of one of a single layer and stacked layers, the third oxide-based layer including a material selected from a group consisting of PE-TEOS oxide, LP-TEOS oxide, phosphosilicate glass (PSG) oxide, borophosphosilicate glass (BPSG) oxide, and ALD oxide.

8. The method of claim 1 , wherein the third insulation layer is etched by employing a gas mixture, the gas mixture including a gas selected from a group consisting of C 4 F 6 , C 5 F 8 , and C 3 F 8 and another gas selected from a group consisting of Ar, He, Xe, and O 2 .

9. The method of claim 1 , wherein the second insulation layer is etched by employing a gas mixture, the gas mixture including CHF 3 and another gas selected from a group consisting of O 2 , Ar, CF 4 , and a combination thereof.

10. The method of claim 1 , further including the step of forming a hard mask layer on the third insulation layer and patterning the hard mask layer prior to forming the second contact holes.

11. The method of claim 10 , wherein the hard mask layer is formed by using a material selected from a group consisting of impurity doped polysilicon, polysilicon that is not doped with impurity, silicon nitride, tungsten, and a combination thereof.

12. The method of claim 11 , wherein the hard mask layer has a thickness ranging from approximately 500 Å to approximately 5,000 Å.

13. The method of claim 1 , wherein the spacers are substantially rectangular in shape.

14. The method of claim 1 , wherein the spacers have substantially vertical sidewalls.

Assignments (10)