Method for forming storage node of capacitor in semiconductor device
View Patent ↗A method for forming a capacitor in a semiconductor device comprises forming an inter-layer layer on a semi-finished substrate; etching the inter-layer insulation layer to form a plurality of first contact holes; forming a first insulation layer on sidewalls of the first contact holes; forming a plurality of storage-node contact plugs filled into the first contact holes; forming a second insulation layer with a different etch rate from the first insulation layer over the storage-node contact plugs; forming a third insulation layer on the second insulation layer; sequentially etching the third insulation layer and the second insulation layer to form a plurality of second contact holes exposing the storage-node contact plugs; and forming the storage node on each of the second contact holes.
1. A method for forming a capacitor in a semiconductor device, the method comprising:
forming a first insulation layer over a substrate;
forming a plurality of first contact holes extending through the first insulation layer;
forming spacers on sidewalls of the first contact holes;
filling storage-node contact plugs into the first contact holes;
forming a second insulation layer over the storage-node contact plugs, wherein the second insulation layer has the same etch characteristics as the first insulation layer;
forming an etch stop layer over the storage-node contact plugs;
forming a sacrificial oxide layer over the etch stop layer;
etching the sacrificial oxide layer and the etch stop layer to form a plurality of second contact holes exposing the storage-node contact holes; and
forming a storage node in each of the second contact holes.
2. The method of claim 1 , wherein the first insulation layer comprises oxide.
3. The method of claim 1 , wherein the spacers comprise nitride.
4. The method of claim 1 , wherein the spacers have a different etch characteristic from that of the first insulation layer.
5. The method of claim 1 , wherein the etch stop layer has the same etch characteristic as the spacers.
6. The method of claim 1 , wherein the height of the storage-node contact plugs is higher than the height of the first insulation layer.
7. The method of claim 1 , wherein the sacrificial oxide layer is formed to have a stack structure including phosphosilicate glass (PSG) and tetraethylorthosilicate (TEOS).
8. The method of claim 1 , further comprising:
planarizing the second insulation layer to be at the same level as the storage-node contact plugs.
9. The method of claim 1 , wherein etching the sacrificial layer and the etch stop layer comprises:
sequentially etching the sacrificial oxide layer and the etch stop layer using an oxide etching process.
10. The method of claim 1 , wherein etching the sacrificial layer and the etch stop layer comprises:
performing an etching process that provides a low etch selectivity of the spacers with respect to the storage-node contact plugs.
11. A method for forming a capacitor in a semiconductor device, the method comprising:
forming a first insulation layer over a substrate;
forming a second insulation layer over the first insulation layer, wherein the second insulation layer and the first insulation layer have a different etch characteristic;
forming a plurality of first contact holes extending through the first insulation layer;
forming spacers on sidewalls of the first contact holes;
filling storage-node contact plugs into the first contact holes;
forming an etch stop layer over the storage-node contact plugs;
forming a sacrificial oxide layer over the etch stop layer;
etching the sacrificial oxide layer and the etch stop layer to form a plurality of second contact holes exposing the storage-node contact holes; and
forming a storage node in each of the second contact holes.
12. The method of claim 11 , wherein forming the first contact holes further comprises forming the first contact holes to extend through the first and the second insulation layers.
13. The method of claim 11 , wherein the spacers have the same etch characteristic as the second insulation layer.
14. The method of claim 11 , wherein the etch stop layer has the same etch characteristic as the second insulation layer.
15. The method of claim 11 , wherein the second insulation layer comprises nitride.
16. The method of claim 1 , further comprising:
selectively recessing predetermined portions of the first insulation layer exposed through the second contact holes by using a different etch selectivity between the first insulation layer and the spacers.
17. The method of claim 16 , wherein the first insulation layer comprises oxide and the spacers comprise nitride, the predetermined portions of the first insulation layer being recessed by performing a high density plasma method using a mixed gas of C 4 F 6 /C 3 F 8 /O 2 /Ar.
18. The method of claim 17 , wherein the mixed gas of C 4 F 6 /C 3 F 8 /O 2 /Ar comprises a ratio of the Ar gas set at approximately 100%, wherein each of the remaining gases has a ratio set at approximately 4% to approximately 10%.
19. The method of claim 17 , wherein the high density plasma method is performed by applying approximately 1,000 W to approximately 2,000 W of source power and approximately 1,500 W to approximately 2,600 W of bias power under a pressure ranging from approximately 15 mtorr to approximately 20 mtorr.
20. The method of claim 16 , wherein selectively recessing the predetermined portions of the first insulation layer employs a high density plasma method using a mixed gas of C 2 F 6 /O 2 .
21. The method of claim 17 , wherein in the mixed gas of C 2 F 6 /O 2 , the C 2 F 6 gas has a ratio of a flow amount set at approximately 100 sccm and the O 2 gas has a ratio of a flow amount ranging from approximately 1 sccm to approximately 4 sccm.
22. The method of claim 17 , wherein the high density plasma method is performed by applying approximately 300 W to approximately 500 W of source power and approximately 200 W to approximately 400 W of bias power under a pressure ranging from approximately 1 mtorr to approximately 10 mtorr.