On-die termination apparatus
View Patent ↗An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding unit for decoding an inputted address to output a plurality of decoding signals to set a termination impedance; an ODT control unit for selectively activating a plurality of pull-up control signals and a multiplicity of pull-down control signals by logically combining the plurality of decoding signals, pull-up test signals and pull-down test signals; and an ODT unit including a plurality of main termination units to test the termination impedance by separately activating the plurality of main termination units based on the plurality of pull-up control signals and the multiplicity of pull-down control signals.
1. An on die termination (ODT) apparatus, comprising:
an extended mode register set decoding unit for decoding an inputted address and outputting a plurality of decoding signals to set a termination impedance;
an ODT control unit for selectively activating a plurality of pull-up control signals and a multiplicity of pull-down control signals by logically combining the plurality of decoding signals, pull-up test signals and pull-down test signals; and
an ODT unit including a plurality of main termination units to test the termination impedance by separately activating the plurality of main termination units based on the plurality of pull-up control signals and the multiplicity of pull-down control signals.
2. The ODT apparatus as recited in claim 1 , wherein each main termination unit includes a PMOS driving unit and an NMOS driving unit.
3. The ODT apparatus as recited in claim 2 , wherein the PMOS driving unit and the NMOS driving unit in said each main termination unit are set to have the same impedance value.
4. The ODT apparatus as recited in claim 2 , wherein the number of the plurality of pull-up control signals is the same as that of PMOS driving units in the plurality of main termination units.
5. The ODT apparatus as recited in claim 4 , wherein each of the PMOS driving units includes:
a plurality of PMOS transistors having terminals connected to a first source voltage terminal and gates for receiving a corresponding one of the pull-up control signals; and
a first termination resistor connected between other terminals of the plurality of PMOS transistors and an output data pad.
6. The ODT apparatus as recited in claim 2 , wherein the number of the pull-down control signals is the same as that of NMOS driving units in the plurality of main termination units.
7. The ODT apparatus as recited in claim 6 , wherein each of the NMOS driving units includes:
a plurality of NMOS transistors having terminals connected to a second source voltage terminal and gates for receiving a corresponding one of the pull-down control signals; and
a second termination resistor connected between other terminals of the plurality of NMOS transistors and an output data pad.
8. The ODT apparatus as recited in claim 1 , wherein the ODT control unit selectively activates the plurality of pull-up control signals when the pull-up test signals are activated, and selectively activates the multiplicity of pull-down control signals when the pull-down test signals are activated.
9. The ODT apparatus as recited in claim 1 , wherein the ODT control unit includes:
a plurality of first logic gates for outputting the plurality of pull-up control signals by logically combining the plurality of decoding signals and the pull-up test signals;
a plurality of second logic gates for logically combining the plurality of decoding signals and the pull-down test signals; and
a plurality of inverters for inverting outputs of the plurality of second logic gates and outputting the inverted signals as the multiplicity of pull-down control signals.
10. The ODT apparatus as recited in claim 9 , wherein each of the first logic gates includes a NAND gate.
11. The ODT apparatus as recited in claim 9 , wherein each of the second logic gates includes a NAND gate.
12. A semiconductor memory device, comprising:
an extended mode register set decoding unit for decoding an inputted address and outputting a plurality of decoding signals to set a termination impedance;
an ODT control unit for selectively activating a plurality of pull-up control signals and a multiplicity of pull-down control signals by logically combining the plurality of decoding signals, pull-up test signals and pull-down test signals; and
an ODT unit including a plurality of main termination units, each main termination unit having a PMOS driving unit and an NMOS driving unit to test the termination impedance by separately activating the plurality of main termination units based on the plurality of pull-up control signals and the multiplicity of pull-down control signals.
13. The semiconductor memory device as recited in claim 12 , wherein the PMOS driving unit and the NMOS driving unit of said each main termination unit are set to have the same impedance value.
14. The semiconductor memory device as recited in claim 12 , wherein the number of the plurality of pull-up control signals is the same as that of the PMOS driving units in the plurality of main termination units.
15. The semiconductor memory device as recited in claim 14 , wherein each of the PMOS driving units includes:
a plurality of PMOS transistors having terminals connected to a first source voltage terminal and gates for receiving a corresponding one of the pull-up control signals; and
a first termination resistor connected between other terminals of the plurality of PMOS transistors and an output data pad.
16. The semiconductor memory device as recited in claim 12 , wherein the number of the pull-down control signals is the same as that of NMOS driving units in the plurality of main termination units.
17. The semiconductor memory device as recited in claim 16 , wherein each of the NMOS driving units includes:
a plurality of NMOS transistors, each NMOS transistor having one terminals connected to a second source voltage terminal and gates for receiving a corresponding one of the pull-down control signals; and
a second termination resistor connected between the other terminals of the plurality of NMOS transistors and an output data pad.
18. The semiconductor memory device as recited in claim 12 , wherein the ODT control unit selectively activates the plurality of pull-up control signals when the pull-up test signals are activated, and selectively activates the plurality of pull-down control signals when the pull-down test signals are activated.
19. The semiconductor memory device as recited in claim 12 , wherein the ODT control unit includes:
a plurality of first NAND gates for outputting the plurality of pull-up control signals by logically combining the plurality of decoding signals and the pull-up test signals;
a plurality of second NAND gates for logically combining the plurality of decoding signals and the pull-down test signals; and
a plurality of inverters for inverting outputs of the plurality of second NAND gates and outputting the inverted signals as the multiplicity of pull-down control signals.