Granted Patent B2

US 7,095,668 · App. 11/032,381 · Granted Aug 22, 2006

Abstract

Claims (26)

1. A main amplifier arranged between a plurality of pairs of local input/output lines and a global input/output line, comprising:

a main amplifier pre-charge unit for pre-charging the main amplifier in response to inputted pre-charge control signals;

an input/output sense amplifier enabled by enable signals for sensing a first data signal transmitted from the plurality of pairs of input/output lines of a plurality of memory banks, amplifying the sensed first data signal, and outputting the amplified first data signal as a second data signal of a first potential level; and

an input/output driver for pull-down or pull-up driving the global input/output line in response to the second data signal from the input/output sense amplifier,

wherein the main amplifier is connected in common to the plurality of pairs of local input/output lines for taking charge of the plurality of memory banks.

2. The main amplifier as set forth in claim 1 , further comprising:

a main amplifier isolation unit for isolating the plurality of memory banks from the main amplifier in response to a main amplifier isolation signal.

3. The main amplifier as set forth in claim 1 , further comprising:

an inverter pre-driver for inverting or non-inverting the second data signal from the input/output sense amplifier and providing the inverted or non-inverted second data signal to the input/output driver.

4. The main amplifier as set forth in claim 1 , wherein the input/output sense amplifier includes two pull-up driving devices and two pull-down driving devices, which are cross-coupled.

5. The main amplifier as set forth in claim 1 , wherein the plurality of memory banks is two memory banks, which are symmetrically opposite to each other.

6. The main amplifier as set forth in claim 1 , wherein the plurality of memory banks is arranged in a stacked structure.

7. A semiconductor device comprising:

a plurality of memory banks each including a plurality of cell matrixes and a plurality of sense amplifier arrays;

a plurality of local input/output line pre-charge units for pre-charging a plurality of pairs of local input/output lines of the plurality of memory banks; and

a plurality of main amplifiers for amplifying data signals from respective pairs of local input/output lines and outputting the amplified data signals to a plurality of global input/output lines,

wherein each of the plurality of main amplifiers comprises:

a main amplifier pre-charge unit for pre-charging the main amplifier in response to inputted pre-charge control signals;

an input/output sense amplifier enabled by enable signals for sensing a first data signal transmitted from respective pairs of input/output lines of respective memory banks, amplifying the sensed first data signal, and outputting the amplified first data signal as a second data signal of a first potential level; and

an input/output driver for full-down or full-up driving respective global input/output lines in response to the second data signal from the input/output sense amplifier, and

wherein the main amplifier is connected in common to a plurality of pairs of local input/output lines for taking charge of a plurality of memory banks.

8. The semiconductor device as set forth in claim 7 , wherein the main amplifier further comprises a main amplifier isolation unit for isolating the plurality of memory banks from the main amplifier in response to a main amplifier isolation signal.

9. The semiconductor device as set forth in claim 7 , wherein the main amplifier further comprises an inverter pre-driver for inverting or non-inverting the second data signal from the input/output sense amplifier and providing the inverted or non-inverted second data signal to the input/output driver.

10. The semiconductor device as set forth in claim 7 , wherein the input/output sense amplifier includes two pull-up driving devices and two pull-down driving devices, which are cross-coupled.

11. The semiconductor device as set forth in claim 7 , wherein the plurality of memory banks is two memory banks, which are symmetrically opposite to each other.

12. The semiconductor device as set forth in claim 7 , wherein the plurality of memory banks is arranged in a stacked structure.

Assignments (8)