Refresh control circuit and method for semiconductor memory device
View Patent ↗A refresh control circuit and a method for refreshing control of a semiconductor memory device are described. The refresh control circuit includes a sense amplifier control circuit configured to generate a sense amplifier driving signal by selectively applying a first delay time and a second delay time (first delay time+third delay time) in response to a sense amplifier enable signal and a refresh command signal (or refresh fail detect signal), and a sense amplifier driver configured to output a sense amplifier driving voltage by applying the first delay time or the second delay time according to a mode.
1. A refresh control circuit for a semiconductor memory device, the circuit comprising:
a sense amplifier control circuit configured to generate a sense amplifier driving signal by selectively applying a first delay time and a second delay time in response to a sense amplifier enable signal and a refresh command signal, wherein the second delay time is a sum of the first delay time and a third delay time having a positive value; and
a sense amplifier driver configured to output a sense amplifier driving voltage by applying the first delay time in a normal operation and the second delay time in a refresh operation,
wherein the sense amplifier control circuit comprises:
a refresh command signal generating unit configured to output a first refresh command signal for selectively applying the first delay time and the second delay time in response to the sense amplifier enable signal and the refresh command signal;
a first sense amplifier driving signal generating unit configured to generate a first sense amplifier driving signal by logically combining the sense amplifier enable signal and the first refresh command signal;
a second sense amplifier driving signal generating unit for delaying the first refresh command signal for a predetermined time and generating a second sense amplifier driving signal; and
a third sense amplifier driving signal generating unit configured to generate a third sense amplifier driving signal by logically combining the first refresh command and the sense amplifier enable signal.
2. The circuit according to claim 1 , wherein the refresh command signal generating unit comprises:
a first delay unit configured to delay the sense amplifier enable signal for the first delay time;
a second delay unit configured to delay the output from the first delay unit for the third delay time;
a first operation unit configured to operate the output signal from the first delay unit and the refresh command signal;
a second operation unit configured to operate the output from the second delay unit and the refresh command signal; and
a third operation unit configured to output the first refresh command signal by applying the first delay time or the second delay time according to the normal operation and the refresh operation by combining the output signals from the first operation unit and the second operation unit and the sense amplifier enable signal.
3. The circuit according to claim 1 , wherein the sense amplifier driver comprises:
a first transistor configured to switch an output of a first sense amplifier driving voltage to a first node in response to the first sense amplifier driving signal;
a second transistor configured to switch an output of a second sense amplifier driving voltage lower than the first sense amplifier driving voltage to the first node in response to the second sense amplifier driving signal; and
a third transistor configured to switch an output of a ground voltage to a second node in response to the third sense amplifier driving signal.
4. A refresh control circuit for a semiconductor memory device, the circuit comprising
a row address comparing unit configured to compare a row address having previously-recorded refresh failure with an internal row address, and to generate a refresh fail detect signal in response to a refresh command signal; and
a sense amplifier control unit configured to output a sense amplifier driving voltage by applying a first delay time in a refresh operation for a general row address and a second delay time in a refresh operation for the row address having the previously-recorded refresh failure in response to the refresh fail detect signal and a sense amplifier enable signal, the second delay time comprising the first delay time and a third delay time.
5. The circuit according to claim 4 , wherein the row address comparing unit comprises:
a storing unit synchronized with the refresh command signal, the storing unit being configured to compare the row address having the previously-recorded failure with the internal row address; and
a refresh fail detect unit synchronized with the refresh command signal, the refresh fail detect unit being configured to output the refresh fail detect signal corresponding to the output signal from the storing unit.
6. The circuit according to claim 5 , wherein the storing unit stores the row address having the refresh failure in a plurality of fuses.
7. The circuit according to claim 5 , wherein the storing unit comprises:
a decoding circuit configured to decode the internal row address; and
a fuse array unit where the row address having the refresh failure is recorded, the fuse array unit for comparing the output signal from the decoding circuit with the row address having the refresh failure recorded in the fuses.
8. The circuit according to claim 5 , wherein the refresh fail detect unit comprises:
a first pulse generator configured to generate a low pulse in response to the refresh command signal;
a precharge unit configured to precharge a common node into VDD level in response to the low pulse;
a latch circuit configured to maintain the precharged VDD level;
a second pulse generator configured to generate a high pulse by logically combining the output signal from the first pulse generator and the output signal from the latch circuit; and
an RS latch circuit configured to latch the output signal from the second pulse generator and an inverted signal of the output signal from the first pulse generator.
9. The circuit according to claim 4 , wherein the sense amplifier control unit comprises:
a sense amplifier control circuit configured to generate a sense amplifier driving signal by selectively applying the first delay time and the second delay time in response to the sense amplifier enable signal and the refresh fail detect signal; and
a sense amplifier driver configured to output the sense amplifier driving voltage by applying the first delay time in the refresh operation for the general row address and the second delay time in the refresh operation for the row address having the previously-recorded failure in response to the sense amplifier driving signal.
10. The circuit according to claim 9 , wherein the sense amplifier control circuit comprises:
a refresh fail detect signal generating unit configured to output a first refresh fail detect signal for selectively applying the first delay time and the second delay time in response to the sense amplifier enable signal and the refresh fail detect signal;
a first sense amplifier driving signal generating unit configured to generate a first sense amplifier driving signal by logically combining the sense amplifier enable signal and the first refresh fail detect signal;
a second sense amplifier driving signal generating unit configured to generate a second sense amplifier driving signal in response to the first refresh fail detect signal; and
a third sense amplifier driving signal generating unit configured to generate a third sense amplifier driving signal by logically combining the first refresh fail detect signal and the sense amplifier enable signal.
11. The circuit according to claim 10 , wherein the refresh fail detect signal generating unit comprises:
a first delay unit configured to delay the sense amplifier enable signal for the first delay time;
a second delay unit configured to delay the output from the first delay unit for the third delay time;
a first operation unit configured to operate the output signal from the first delay unit and the refresh fail detect signal;
a second operation unit configured to operate the output from the second delay unit and the refresh fail detect signal; and
a third operation unit configured to output the first refresh fail detect signal by applying the first delay time or the second delay time according to the refresh operation for the general row address and the refresh operation for the row address having the previously-recorded refresh failure by combining the output signals from the first operation unit and the second operation unit and the sense amplifier enable signal.
12. The circuit according to claim 10 , wherein the sense amplifier driver comprises:
a first transistor configured to switch an output of a first sense amplifier driving voltage to a first node in response to the first sense amplifier driving signal;
a second transistor configured to switch an output of a second sense amplifier driving voltage lower than the first sense amplifier driving voltage to the first node in response to the second sense amplifier driving signal; and
a third transistor configured to switch an output of a ground voltage to a second node in response to the third sense amplifier driving signal.
13. A refresh control method for a semiconductor memory device, the method comprising:
generating an internal row address for a refresh operation in response to a refresh command signal;
generating a refresh fail detect signal by comparing a row address having previously-recorded failure with the internal row address in a refresh operation; and
driving a sense amplifier by supplying an initial sense amplifier driving voltage for the row address having the previously-recorded refresh failure longer than for a general row address in response to the refresh fail detect signal in the refresh operation.
14. The method according to claim 12 , further comprising a step for recording the row address having the refresh failure obtained through a test in fuses.