Process, voltage, temperature independent switched delay compensation scheme
View Patent ↗A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine delay for modeling a coarse delay element, a counter for controlling the adjustable fine delay to a value which is substantially the same as that of a coarse delay element, a circuit for applying a representation of the system clock to the delay compensation circuit, and a circuit for applying the fine delay count from the counter to the controller for adjusting the fine delay line of the main delay line to a value which is substantially the same as that of a coarse delay element of the main delay line.
1. A circuit for modeling a coarse delay element with a plurality of fine delay elements, the circuit comprising:
first and second parallel delay paths for receiving a clock signal, the first path including
a plurality of fine delay elements, and the second path including the same number of fine delay elements as the first path and a coarse delay element, each of the fine delay elements within the second path having a fixed delay for providing an output signal delayed relative to a received input signal by a constant duration of time;
a phase detector for receiving first and second clock delay signals from the first and second delay paths respectively, for detecting a phase difference between the first and second clock delay signals, and for providing the phase difference to a counter; and
a decoder for receiving a signal from the counter, the decoder being connected to the fine delay elements within the first delay path for adjusting a delay provided by the first delay path.
2. The circuit according to claim 1 , wherein a delay provided by the first delay path is selectable by binary logic signals.
3. The circuit according to claim 1 , wherein the fixed delay of the fine delay elements within the second delay path corresponds to an intrinsic delay substantially equal to a minimum delay of the fine delay elements within the first delay path.
4. The circuit according to claim 1 , wherein the first delay path consists of fine delay elements.
5. The circuit according to claim 1 , wherein the phase detector comprises a flip-flop circuit.
6. The circuit according to claim 1 , wherein the counter is a count-up count-down type counter.
7. The circuit according to claim 1 further comprising a Delay Lock Loop (DLL), the DLL comprising:
a coarse delay line for receiving a system clock;
a fine delay line coupled to an output of the coarse delay line for providing a delay clock signal; and
a main phase detector for receiving the system clock and the delay clock signals, the main phase detector coupled to a main fine counter being adjusted by the signal from the counter for adjusting the fine delay line and a main coarse counter for adjusting a delay provided by the coarse delay line.
8. The circuit according to claim 7 , wherein the count from the counter is provided to the main fine counter.
9. The circuit according to claim 8 , wherein the count provided by the counter to the main fine counter is substantially equal to a number of delays provided by the fine delay elements within the fine delay line that correspond to a delay provided by a coarse delay element within the coarse delay line.
10. A circuit for modeling a coarse delay element with a plurality of fine delay elements, the circuit comprising:
first and second parallel delay paths for receiving a clock signal, the first path including
a plurality of fine delay elements, and the second path including the same number of fine delay elements as the first path and a coarse delay element, each of the fine delay elements within the second path having a fixed delay for providing an output signal delayed relative to a received input signal by a constant duration of time;
a phase detector for receiving the first and second clock delay signals from the first and second delay paths respectively, and for detecting a phase difference between the first and second clock delay signals; and
a counter for receiving the phase difference from the phase detector and for generating a signal for adjusting a delay provided by the first delay path delay.
11. The circuit according to claim 10 , wherein a delay provided by the first delay path is selectable by binary logic signals.
12. The circuit according to claim 10 , wherein the fixed delay of the fine delay elements within the second delay path corresponds to an intrinsic delay substantially equal to a minimum delay of the fine delay elements within the first delay path.
13. The circuit according to claim 10 , wherein the first delay path consists of fine delay elements.
14. The circuit according to claim 10 , wherein the phase detector comprises a flip-flop circuit.
15. The circuit according to claim 10 , wherein the counter is a count-up count-down type counter.
16. The circuit according to claim 10 further comprising a Delay Lock Loop (DLL), the DLL comprising:
a coarse delay line for receiving a system clock;
a fine delay line coupled to an output of the coarse delay line for providing a delay clock signal; and
a main phase detector for receiving the system clock and the delay clock signals, the main phase detector coupled to a main fine counter being adjusted by the signal from the counter for adjusting the fine delay line and a main coarse counter for adjusting a delay provided by the coarse delay line.
17. The circuit according to claim 16 , wherein the count is provided to the main fine counter.
18. The circuit according to claim 16 , wherein the signal provided by the counter to the main fine counter is substantially equal to a number of delays provided the fine delay elements within the fine delay line that correspond to a delay provided by a coarse delay element within the coarse delay line.
19. A delay lock loop (DLL) comprising a circuit for modeling a coarse delay element with a plurality of fine delay elements, the circuit comprising:
first and second parallel delay paths for receiving a clock signal, the first path including a plurality of fine delay elements and the second path including the same number of fine delay elements as the first path and a coarse delay element, each of the fine delay elements within the second path having a fixed delay for providing an output signal delayed relative to a received input signal by a constant duration of time;
a phase detector for receiving first and second clock delay signals from the first and second delay paths respectively, for detecting a phase difference between the first and second clock delay signals, and for providing the phase difference to a counter; and
a decoder for receiving a signal from the counter, and for providing signals to the first delay path for adjusting a delay provided by the first delay path.