Charge pump for PLL/DLL
View Patent ↗A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The charge pump further includes a pull-up circuit and a pull-down circuit coupled to the operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.
1. A delay locked loop comprising:
a voltage controlled delay circuit having an input and an output;
a phase detector detecting phase difference between a feedback clock derived from the output of the voltage controlled delay circuit and the input to the voltage controlled delay circuit;
a loop filter providing a control voltage to the voltage controlled delay circuit; and
a charge pump comprising:
a pull-up circuit which generates pull-up current to increase voltage at a charge pump output, the charge pump in electrical communication with the loop filter through the charge pump output;
a pull-down circuit which generates pull-down current to decrease voltage at the charge pump output;
an operation amplifier having two inputs and an output, the operational amplifier configured to reduce phase error, one of the inputs of the operational amplifier connected to a charge pump output node; and
a reference current source having a plurality of select transistors and a plurality of mirror master transistors, said mirror master transistors coupled to slave transistors of a selected one of said pull-up circuit and said pull-down circuit to mirror variable current in said slave transistors.
2. The delay locked loop as claimed in claim 1 wherein the feedback clock is derived from the output of the voltage controlled delay circuit through a replica delay circuit.
3. The delay locked loop as claimed in claim 1 wherein the phase detector provides signals to control the charge pump pull-up circuit and pull-down circuit.
4. The delay locked loop as claimed in claim 1 wherein the plurality of select transistors and the plurality of mirror master transistors include a programmable array of field-effect transistors.
5. The delay locked loop as claimed in claim 1 wherein each one of the plurality of select transistors is coupled to one of the plurality of mirror master transistors to selectively enable or disable said one of the plurality of mirror master transistors.
6. The delay locked loop as claimed in claim 5 wherein said one of the plurality of select transistors is connected between a power supply and said one of the plurality of mirror master transistors.
7. The delay locked loop as claimed in claim 6 wherein said power supply is the positive power supply Vdd.
8. The delay locked loop as claimed in claim 6 wherein the gates and drains of the plurality of mirror master transistors are commonly connected to a current reference node which sets the charge pump current.
9. The delay locked loop as claimed in claim 6 wherein the plurality of select transistors and the plurality of mirror master transistors are PMOS transistors.
10. The delay locked loop as claimed in claim 1 wherein at least one of the plurality of select transistors are controlled by registers.
11. The delay locked loop as claimed in claim 1 wherein at least one of the plurality of select transistors are controlled by fuses.
12. The delay locked loop as claimed in claim 1 wherein at least one of the plurality of select transistors are controlled by mask programming.