Integrated circuit with signal bus formed by cell abutment of logic cells
View Patent ↗An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells.
1. An integrated circuit comprising:
at least two logic cells; and
a sleep signal bus formed by cell abutment of the at least two logic cells and configured to receive a sleep signal and distribute the sleep signal to each of the at least two logic cells.
2. The integrated circuit of claim 1 wherein the sleep signal bus spans across the at least two logic cells.
3. The integrated circuit of claim 1 wherein the sleep signal bus is formed from a conductive layer.
4. The integrated circuit of claim 3 wherein the conductive layer comprises a polycrystalline silicon layer.
5. The integrated circuit of claim 1 further comprising a sleep pin coupled to the sleep signal bus and configured to receive the sleep signal.
6. The integrated circuit of claim 1 further comprising sleep circuitry coupled to the at least two logic cells and configured to receive the sleep signal from the sleep signal bus and to control power consumption in the at least two logic cells based on the sleep signal.
7. The integrated circuit of claim 6 wherein the sleep circuitry comprises one or more sleep transistors.
8. The integrated circuit of claim 7 wherein a drain of the one or more sleep transistors is formed from a semiconductor layer.
9. The integrated circuit of claim 7 wherein the one or more sleep transistors comprise NMOS transistors.
10. The integrated circuit of claim 7 wherein the one or more sleep transistors comprise PMOS transistors.
11. A method comprising:
receiving a sleep signal using a sleep signal bus formed by cell abutment of at least two logic cells; and
distributing the sleep signal to each of the at least two logic cells.
12. The method of claim 11 wherein the sleep signal bus spans across the at least two logic cells.
13. The method of claim 11 wherein distributing the sleep signal comprises using the sleep signal bus formed from a conductive layer.
14. The method of claim 13 wherein the conductive layer comprises a polycrystalline silicon layer.
15. The method of claim 11 further comprising receiving the sleep signal from a sleep pin coupled to the sleep signal bus.
16. The method of claim 11 wherein distributing the sleep signal comprises using sleep circuitry configured to control the power consumption in the at least two logic cells.
17. The method of claim 16 wherein the sleep circuitry comprises one or more sleep transistors.
18. The method of claim 17 wherein a drain of the one or more sleep transistors is formed from a semiconductor layer.
19. The method of claim 17 wherein the one or more sleep transistors comprise NMOS transistors.
20. The method of claim 17 wherein the one or more sleep transistors comprise PMOS transistors.
21. A standard cell library comprising:
at least two logic cells; and
a sleep signal bus formed by cell abutment of the at least two logic cells and configured to receive a sleep signal and distribute the sleep signal to each of the at least two logic cells.
22. The standard cell library of claim 21 further comprising sleep circuitry coupled to the at least two logic cells.
23. The standard cell library of claim 22 wherein said sleep circuitry is configured to receive the sleep signal from the sleep signal bus and to control power consumption in the at least two logic cells based on the sleep signal.