Apparatus and method for self-refreshing dynamic random access memory cells
View Patent ↗A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.
1. A method for low power refreshing a dynamic random access memory (DRAM) having cells arranged in rows and columns, comprising:
refreshing the cells in a one cell-per-bit mode at a first frequency during a normal mode of operation where the cells are read and written in the one cell-per-bit mode;
entering a self-refresh mode for reducing refresh power consumption;
generating refresh addresses including a starting refresh address for selecting a first row of cells to be refreshed, by an address counter;
executing a dummy refresh cycle in response to a comparison between the starting address and a predetermined address;
refreshing the cells in a two cell-per-bit mode at a second frequency lower than the first frequency during the self-refresh mode in response to the refresh addresses and beginning at the starting refresh address; and,
exiting the self-refresh mode to resume the normal mode of operation.
2. The method of claim 1 , wherein entering the self-refresh mode includes receiving a command to enter the self-refresh mode.
3. The method of claim 1 , wherein entering the self-refresh mode includes detecting the starting refresh address of the address counter for determining if the starting refresh address is to be changed.
4. The method of claim 3 , wherein detecting includes comparing the starting refresh address to the predetermined address, and changing the starting refresh address if the starting refresh address mismatches the predetermined address.
5. The method of claim 4 , wherein comparing includes comparing a lowest significant bit of the starting refresh address to the predetermined address.
6. The method of claim 1 , wherein the dummy refresh cycle is executed if the starting refresh address mismatches the predetermined address in the comparison.
7. The method of claim 6 , wherein executing the dummy refresh cycle includes incrementing the address counter to change the starting refresh address to a new starting refresh address before refreshing the cells in the two cell-per-bit mode.
8. The method of claim 7 , wherein executing the dummy refresh cycle includes controlling an address decoder to disregard the starting refresh address.
9. The method of claim 1 , wherein refreshing the cells in a two cell-per-bit mode includes retaining main data of the cells coupled to first wordlines and overwriting data of the cells coupled to second wordlines with additional data complementary to the main data.
10. The method of claim 1 , wherein entering the self-refresh mode includes executing a burst refresh cycle for refreshing all the cells of the DRAM in the two cell-per-bit mode.
11. The method of claim 10 , wherein the DRAM includes N rows of cells, where N is an integer value, and entering the self-refresh mode further includes generating N refresh clock pulses.
12. The method of claim 11 , wherein executing the burst refresh cycle includes counting the number of refresh clock pulses and terminating the burst refresh cycle when the N refresh clock pulses have been counted.
13. The method of claim 12 , wherein refreshing the cells in the two cell-per-bit mode begins after the burst refresh cycle has been terminated.
14. The method of claim 10 , wherein the cells of the DRAM are refreshed during the burst refresh cycle at a frequency higher than the second frequency.
15. The method of claim 1 , wherein exiting the self-refresh mode includes executing a burst refresh cycle for refreshing all the cells of the DRAM in the one cell-per-bit mode.
16. The method of claim 15 , wherein the DRAM includes N rows of cells, where N is an integer value, and exiting the self-refresh mode further includes generating N refresh clock pulses.
17. The method of claim 16 , wherein executing the burst refresh cycle includes counting the number of refresh clock pulses and terminating the burst refresh cycle when the N refresh clock pulses have been counted.
18. The method of claim 15 , wherein the cells of the DRAM are refreshed during the burst refresh cycle at a frequency higher than the second frequency.