Synchronization circuit and method with transparent latches
View Patent ↗A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
1. A skew compensation circuit for compensating a phase difference between a master clock signal and an output clock signal transferring data, the skew compensation circuit comprising:
a master clock input for receiving a master clock signal;
an output clock input for receiving an output clock signal the output clock signal being distinct from the master clock signal;
a first transparent latch for receiving the data, the first transparent latch being enabled by the master clock signal;
a second transparent latch for receiving the data from the first transparent latch, the second transparent latch being enabled by a delayed output clock signal, the delayed output clock signal being a delayed version of the output clock signal.
2. The skew compensation circuit of claim 1 , wherein the delayed output clock signal includes an insertion delay and the output clock signal is a delay locked loop version of the delayed output clock signal with the insertion delay removed.
3. The skew compensation circuit of claim 1 , wherein a phase difference between the input clock signal and the output clock signal is less than or equal to one hundred and eighty degrees.
4. The skew compensation circuit of claim 1 , wherein the input clock signal is a K# clock signal of a master clock pair and the output clock signal is a C# clock signal of a data clock pair.
5. The skew compensation circuit of claim 1 , wherein each of the first and second transparent latches passes received data when open and hold a last data received when closed.
6. The skew compensation circuit of claim 5 , wherein the first transparent latch is open when the input clock signal is logic ‘1’ and closed when the input clock signal is logic ‘0’.
7. The skew compensation circuit of claim 6 wherein the second transparent latch is open when the delayed output clock signal is logic ‘1’ and closed when the delayed output clock signal is logic ‘0’.
8. A method for compensating a phase difference between a master clock signal and an output clock signal transferring data, the method comprising:
receiving a master clock signal;
receiving an output clack signal, the output clock signal being distinct from the master clock signal;
receiving the data by a first transparent latch enabled by the master clock signal; and
receiving data from the first transparent latch by a second transparent latch enabled by a delayed output clock signal, the delayed output clock signal being a delayed version of the output clock signal.
9. The method of claim 8 , wherein the delayed output clock signal includes an insertion delay and the output clock signal is a delay lock loop version of the delayed output clock signal with the insertion delay removed.
10. The method of claim 8 , wherein a phase difference between the input clock signal and the output clock signal is less than or equal to one hundred and eighty degrees.
11. The method of claim 8 , wherein the input clock signal is a K# clock signal of a master clock pair and the output clock signal is a C# clock signal of a data clock pair.
12. The method of claim 8 , wherein each of the first transparent latch and the second transparent latch passes received data when open and hold a last data received when closed.
13. The method of claim 12 , wherein the first transparent latch is open when the input clock signal is logic ‘1’ and closed when the input clock signal is logic ‘0’.
14. The method of claim 13 , wherein the second transparent latch is open when the delayed output clock signal is logic ‘1’ and closed when the delayed output clock signal is logic ‘0’.