Flash multi-level threshold distribution scheme
View Patent ↗A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.
1. A Flash memory device comprising:
a memory array having at least one memory cell programmable to have one of a first cell state, a second cell state, and an erase state,
the first cell state corresponding to a first programmed state and having a first threshold voltage in a first threshold voltage range between a lower voltage limit having a negative voltage and an upper voltage limit having a positive voltage,
the second cell state corresponding to a second programmed state and having a second threshold voltage within a second threshold voltage range lower than the first threshold voltage range,
the erase state having an erase threshold voltage range lower than the second threshold voltage range.
2. The Flash memory device of claim 1 , wherein the at least one memory cell is programmable to a third programmed state having a third threshold voltage range higher than the first threshold voltage range.