Flash memory program inhibit scheme
View Patent ↗A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.
1. A flash device having a NAND string coupled to a bitline set to a program inhibit voltage for precharging memory cell channels when all word lines of the NAND string are driven to at least a first voltage level, the NAND string comprising:
a selected memory cell having a selected word line increased to a programming voltage level;
an upper memory cell between the selected memory cell and the bitline having an upper selected word line reduced to a second voltage level higher than VSS while the selected word line is at the programming voltage level; and,
a lower memory cell between the selected memory cell and a source line of the NAND string having a lower selected word line reduced to a third voltage level while the selected word line is at the programming voltage level.
2. The flash device of claim 1 , wherein all word lines of the NAND string are driven to a first pass voltage level.
3. The flash device of claim 2 , wherein the second voltage and the third voltage is a decoupling voltage.
4. The flash device of claim 1 , wherein the second voltage is a decoupling voltage and the third voltage is VSS.
5. The flash device of claim 1 , wherein all the word lines of the NAND string include
lower word lines connected to lower memory cells between the selected memory cell and the source line of the NAND string,
upper word lines connected to upper memory cells between the selected memory cell and the bitline.
6. The flash device of claim 5 , wherein the upper word lines are driven to a first pass voltage level while the lower word lines are driven to a second pass voltage level different from the first pass voltage level for precharging the memory cell channels.
7. The flash device of claim 6 , wherein the second pass voltage level is less than the first pass voltage level.
8. The flash device of claim 7 , wherein the second voltage is a decoupling voltage and the third voltage is VSS.
9. A NAND flash device comprising:
row circuitry for driving word lines with voltages between VSS and a programming voltage level;
bitline circuits for biasing bit lines to one of a program inhibit voltage and a program enable voltage;
a memory array having NAND strings connected to bit lines and source lines, and having memory cells connected to the word lines, each NAND string inhibited from programming being coupled to a bitline set to the program inhibit voltage for precharging memory cell channels when all word lines of the NAND string are driven to at least a first voltage level, and the NAND strings including
a selected memory cell having a selected word line increased to a programming voltage level;
an upper memory cell adjacent the selected memory cell and having an upper selected word line reduced to a second voltage level higher than VSS while the selected word line is at the programming voltage level; and,
a lower memory cell adjacent the selected memory cell and having a lower selected word line reduced to a third voltage level while the selected word line is at the programming voltage level.
10. The NAND flash device of claim 9 , wherein all word lines of the NAND string are driven to a first pass voltage level.
11. The NAND flash device of claim 10 , wherein the second voltage and the third voltage is a decoupling voltage.
12. The NAND flash device of claim 9 , wherein the second voltage is a decoupling voltage and the third voltage is VSS.
13. The NAND flash device of claim 9 , wherein all the word lines of the NAND string include
lower word lines connected to lower memory cells between the selected memory cell and the source line of the NAND string,
upper word lines connected to upper memory cells between the selected memory cell and the bitline.
14. The NAND flash device of claim 13 , wherein the upper word lines are driven to a first pass voltage level while the lower word lines are driven to a second pass voltage level different from the first pass voltage level for precharging the memory cell channels.
15. The NAND flash device of claim 14 , wherein the second pass voltage level is less than the first pass voltage level.
16. The NAND flash device of claim 15 , wherein the second voltage is a decoupling voltage and the third voltage is VSS.