Granted Patent B2

US 7,778,107 · App. 12/416,512 · Granted Aug 17, 2010

Abstract

Claims (46)

1. An apparatus for detecting whether a first multi-bit block address portion of a first address is different from a second multi-bit block address portion of a second address in that at least one bit of the first multi-bit block address portion of the first address is different from at least one corresponding bit of the second multi-bit block address portion of the second address, the apparatus comprising:

for each bit of the first multi-bit block address portion, a respective address detection circuit for detecting whether the bit is different from the corresponding bit of the second multi-bit block address portion; and

a combining circuit for combining outputs of the address detection circuits to produce an output indicative of whether the first multi-bit block address portion of the first address is different from the second multi-bit block address portion of the second address; and

N inputs, where N is the number of bits in the first multi-bit block address portion, and also is the number of bits in the second multi-bit block address portion;

wherein for each input of the N inputs, the apparatus is configured to receive through the input a bit of the first multi-bit block address portion followed by the corresponding bit of the second multi-bit block address portion; and

wherein each address detection circuit comprises:

a rise detecting circuit for detecting rising address transitions;

a fall detecting circuit for detecting falling address transitions; and

a combining circuit for combining outputs of the rise detecting circuit and the fall detecting circuit.

2. The apparatus of claim 1 wherein each first detecting circuit comprises:

an inverter and a delay element connected together in sequence; and

a NAND gate having a first input connected to receive one of the N inputs, the NAND gate having a second input connected to receive the one of the N inputs after inversion by the inverter and delay by the delay element, and

each second detecting comprises:

an inverter and a delay element; and

a NAND gate having a first input connected to receive one of the N inputs address after inversion by the inverter, the NAND gate having a second input connected to receive the one of the N inputs after delay by the delay element.

3. The apparatus of claim 1 further comprising:

for each of the N inputs, a respective sub-address register that produces a respective registered address output;

wherein for each bit of the first multi-bit block address, the respective address detection circuit detects transitions in the bit by processing the respective registered address output.

4. The apparatus of claim 3 wherein for each of the N inputs, the respective sub-address register comprises:

an SR (set-reset) latch connected to receive the input; and

an enable circuit for enabling latching to the SR latch.

5. A flash device comprising the apparatus of claim 1 .

6. The flash device of claim 3 wherein the flash device is a NAND flash device.

7. A method for detecting whether a first multi-bit block address portion of a first address is different from a second multi-bit block address portion of a second address in the sense that at least one bit of the first multi-bit block address portion of the first address is different from at least one corresponding bit of the second multi-bit block address portion of the second address, the method comprising:

for each bit of the first multi-bit block address portion, detecting whether the bit is different from the corresponding bit of the second multi-bit block address portion; and

combining results of the detecting to produce an output indicative of whether the first multi-bit block address portion of the first address is different from the second multi bit block address portion of the second address; and

N is the number of bits in the first multi-bit block address portion, and also is the number of bits in the second multi-bit block address portion;

the method further comprising:

for each of the N bits of the first multi-bit block address portion, receiving a respective signal comprising the bit of the first multi-bit block address portion followed by the corresponding bit of the second multi-bit block address portion; and

wherein for each bit of the multi-bit block address, detecting comprises:

detecting rising address transitions;

detecting failing address transitions; and

combining results of detecting rising address transitions and detecting falling address transitions.

8. The method of claim 7 wherein for each bit of the multi-bit block address:

detecting rising address transitions comprises:

inverting and delaying the respective signal to produce an inverted and delayed signal;

combining the respective signal and the inverted and delayed signal according to a NAND logic function;

detecting falling address transitions comprises:

inverting the respective signal to produce an inverted signal;

delaying the respective signal to produce a delayed signal combining the inverted signal and the delayed signal according to a NAND logic function.

9. The method of claim 7 further comprising:

registering each of the N input signals to produce a respective registered address output;

wherein for each bit of the first multi-bit block address, detecting transitions comprises detecting transitions in the respective registered address output.

10. The method of claim 9 wherein registering each of the N input signals to produce a respective registered address output comprises SR latching each of the N input signals under control of an enable input.

11. The method of claim 7 used in a flash device.

12. The method of claim 7 used in a NAND flash device.

Assignments (6)