Granted Patent B2

US 8,064,260 · App. 12/903,271 · Granted Nov 22, 2011

Abstract

Claims (26)

1. A flash memory device comprising:

a first section including flash memory for storing data; and

a second section including:

i) at least first and second pumping circuits having outputs, the second section being a peripheral circuit section, the first pumping circuit being configured to increase voltage produced therefrom under control of at least a first oscillation signal, and the second pumping circuit being configured to increase voltage produced therefrom under control of at least a second oscillation signal, different from the first oscillation signal;

ii) first and second regulator circuits; and

iii) first and second oscillators for providing the first and second oscillation signals respectively, the first regulator circuit coupled to the first pumping circuit output, the first oscillator configured to receive an outputted voltage of the first regulator circuit, the second regulator circuit coupled to the second pumping circuit output, and the second oscillator configured to receive an outputted voltage of the second regulator circuit, and

iv) wherein the first pumping circuit is configured to produce, at the first pumping circuit output, a first voltage required for carrying out a first type of memory operation, and the second pumping circuit being configured to produce, at the second pumping circuit output, a second voltage required for carrying out a second type of memory operation different than the first type of memory operation, and wherein the second pumping circuit pumps up from one transistor threshold voltage (Vtn) less than a voltage level of the first voltage.

2. The flash memory device as claimed in claim 1 , wherein the first and second types of memory operations are read and program operations respectively.

3. The flash memory device as claimed in claim 1 , wherein the second pumping circuit cooperatively employs the first pumping circuit to pump up from a voltage substantially greater than a voltage V DD .

4. The flash memory device as claimed in claim 3 , wherein the voltage V.sub.DD is 1.5V or less.

5. The flash memory device as claimed in claim 1 , wherein the first regulator circuit includes at least two voltage dividers and an operational amplifier.

6. The flash memory device as claimed in claim 1 , wherein the first regulator circuit includes trimming control circuitry.

7. The flash memory device as claimed in claim 1 wherein the flash memory comprises an array of memory cells.

8. The flash memory device as claimed in claim 1 , wherein at least one of the first and second pumping circuits comprises a Dickson charge pump.

9. The flash memory device as claimed in claim 1 , further comprising at least one additional pumping circuit working in parallel with the first pumping circuit to provide for increased current, the at least one additional pumping circuit being at least substantially similar to the first pumping circuit.

10. The flash memory device as claimed in claim 1 , wherein the first and second oscillators comprise chains of inverters.

11. A method of producing voltages in a flash memory device having a first section including flash memory for storing data, and also having a second section that includes

i) at least first and second pumping circuits, and

ii) first and second oscillators, and the method comprising: supplying, within the flash memory device, a first voltage at a first voltage level to the first pumping circuit; producing, at an output of the first pumping circuit, a second voltage at a second voltage level that is higher than the first voltage level, the second voltage required for carrying out a first type of memory operation associated with the flash memory; producing, at an output of the second pumping circuit, and

iii) a third voltage by cooperatively employing the first pumping circuit to pump up from a voltage greater than the first voltage, the third voltage at a third voltage level that is higher than the second voltage level, the third voltage required for carrying out a second type of memory operation associated with the flash memory, the second type of memory operation different than the first type of memory operation; providing, from the first oscillator, an at least one oscillation signal to the first pumping circuits, the second voltage level increasing under control of the at least one oscillation signal; and providing, from the second oscillator, an at least another oscillation signal to the second pumping circuit, the at least another oscillation signal different than the at least one oscillation signal, and the third voltage level increasing under control of the at least another oscillation signal.

iv) wherein the first pumping circuit is configured to produce, at the first pumping circuit output, a first voltage required for carrying out a first type of memory operation, and the second pumping circuit being configured to produce, at the second pumping circuit output, a second voltage required for carrying out a second type of memory operation different than the first type of memory operation, and wherein the second pumping circuit pumps up from one transistor threshold voltage (Vtn) less than a voltage level of the first voltage.

12. The method as claimed in claim 11 , wherein the first and second types of memory operations are read and program operations respectively.

13. The method as claimed in claim 11 , wherein the first voltage is a voltage V DD .

14. The method as claimed in claim 13 , wherein the voltage V.sub.DD is 1.5V or less.

15. The method as claimed in claim 11 , wherein the second type of memory operation is an erase operation.

16. The method as claimed in claim 15 , further comprising carrying out the erase operation.

Assignments (8)