Method of repairing a failed wordline
View Patent ↗A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.
1. A method for repairing a failed wordline, the method comprising:
storing address signals in an address storage;
controlling an address repaired in a wordline segment to be selected;
applying a power supply voltage to a select signal line and applying a ground voltage to a gate of a depletion-type NMOS transistor in a local decoder circuit based upon the address;
turning on a NMOS transistor in a global decoder circuit; and
applying the power supply voltage to a global word line and a local wordline through the NMOS transistor and the depletion type NMOS transistor, such that memory cells connected to the local word line are erase-prohibited.
2. The method of claim 1 , wherein the address storage further comprises a fuse box.