Patent Assignment
Reel/Frame 054371/0157
Release of Security Interest
Recorded: 2020-11-10
Pages: 74
Assignor
CPPIB CREDIT INVESTMENTS INC.
Executed: 2020-10-28
Assignee
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
515 LEGGET DRIVE, SUITE 704, OTTAWA, K2K 3G4, CANADA
Covered Properties
(51)
Methods of Fabricating Conductive Lines in Integrated Circuits Using Insulating Sidewall Spacers and Conductive Lines So Fabricated
Patent:
6,066,556 →
Application:
09/184,918 →
Contact Structure of Semiconductor Memory Device for Reducing Contact Related Defect and Contact Resistance and Method for Forming the Same
Patent:
6,072,242 →
Application:
09/209,649 →
Nonvolatile Memory Devices Having Alternative Programming
Patent:
6,434,052 →
Application:
09/222,044 →
Method for Fabricating a Dram Cell Capacitor Including Etching Upper Conductive Layer with Etching Byproduct Forming a Etch Barrier on the Conductive Pattern
Patent:
6,238,970 →
Application:
09/343,353 →
Trench Isolation Method for Semiconductor Integrated Circuit
Patent:
6,268,265 →
Application:
09/346,450 →
Method for Fabricating a Semiconductor Memory Device and the Structure Thereof
Patent:
6,337,267 →
Application:
09/347,821 →
Semiconductor Device Having Triple-Well
Patent:
6,225,199 →
Application:
09/348,381 →
Devices for Controlling Temperature Indications in Integrated Circuits Using Adjustable Threshold Temperatures
Patent:
6,442,500 →
Application:
09/359,438 →
Metallization Process for Manufacturing Semiconductor Devices
Patent:
6,335,284 →
Application:
09/386,360 →
Multilayer Passivation Process for Forming Air Gaps Within a Dielectric Between Interconnections
Methods of Forming Self-Aligned Contact Pads on Electrically Conductive Lines
Patent:
6,268,252 →
Application:
09/442,523 →
Method of Manufacturing a Capacitor Having Oxide Layers with Different Impurities and Method of Fabricating a Semiconductor Device Comprising the Same
Patent:
6,376,303 →
Application:
09/499,295 →
Method of fabricating self-aligning stacked capacitor using electroplating method
Patent:
6,255,187 →
Application:
09/551,524 →
Data input circuit of semiconductor memory device
Patent:
6,324,119 →
Application:
09/557,619 →
Method of fabricating floating gates in semiconductor device
Patent:
6,342,451 →
Application:
09/558,683 →
Method of Forming T-Shaped Isolation Layer, Method of Forming Elevated Salicide Source/Drain Region Using the Same, and Semiconductor Device Having T-Shaped Isolation Layer
Patent:
6,383,877 →
Application:
09/573,268 →
Planarization Method of Insulating Layer for Semiconductor Device
Patent:
6,423,639 →
Application:
09/603,202 →
Trench Isolation Method for Semiconductor Integrated Circuit
Patent:
6,436,611 →
Application:
09/611,799 →
Semiconductor Memory Device Having a Plurality of Laser Fuses
Patent:
6,448,626 →
Application:
09/672,924 →
Trench isolation structure, semiconductor device having the same, and trench isolation method
Patent:
6,331,469 →
Application:
09/684,822 →
Non-Volatile Semiconductor Memory Device Capable of Reducing Read Time
Patent:
6,434,042 →
Application:
09/703,393 →
Method for Fabricating a Capacitor of a Semiconductor Device and a Capacitor Made Thereby
Patent:
6,391,736 →
Application:
09/704,763 →
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
Level-Shifting Reference Voltage Source Circuits and Methods
Semiconductor Memory Device Having a Memory Block with a Decreased Capacitance
Non-Volatile Semiconductor Memory Device
Patent:
6,466,478 →
Application:
09/847,115 →
Bit Line Sensing Control Circuit for a Semiconductor Memory Device and Layout of the Same
Method of Forming Interlevel Dielectric Layer of Semiconductor Device
Methods of Forming Self-Aligned Contact Pads on Electrically Conductive Lines
Trench Isolatoin Regions Having Trench Liners with Recessed Ends
Semiconductor Memory Device with Redundancy Logic Cell and Repair Method
Wafer Polishing Slurry and Chemical Mechanical Polishing (Cmp) Method Using the Same
Pattern Formation Method Using Two Alternating Phase Shift Masks
Reference Voltage Generator
Memory Cell Decoder Not Including a Charge Pump
Method of Forming Semiconductor Device Having a Gaa Type Transistor
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer and Method of Manufacturing the Same
Method for Depositing a Tungsten Silicide Layer
Semiconductor Device Having Trench Isolation Structure and Method of Forming Same
Method of Forming T-Shaped Isolation Layer, Method of Forming Elevated Salicide Source/Drain Region Using the Same, and Semiconductor Device Having T-Shaped Isolation Layer
Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Recessed Gate Electrode Mos Transistors Having a Substantially Uniform Channel Length Across a Width of the Recessed Gate Electrode and Methods of Forming Same
Method of Repairing a Failed Wordline
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer and Method of Manufacturing the Same
Semiconductor Memory Device
Semiconductor Device Having No Cracks in One or More Layers Underlying a Metal Line Layer
Semiconductor Device Having Metal Lines with Slits
Semiconductor Device Having Metal Lines with Slits
Semiconductor Device Having Metal Lines with Slits
Integrated Circuit Chip Having Anti-Moisture-Absorption Film at Edge Thereof and Method of Forming Anti-Moisture-Absorption Film
Patent:
46,549 →
Application:
14/025,203 →
Related Assignments
(13)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 24, 2010
From: SAMSUNG ELECTRONICS CO., LTD.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 025420/0450 →
Assignment of Assignor's Interest
Nov 24, 2010
From: SAMSUNG ELECTRONICS CO., LTD.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 025420/0349 →
Assignment of Assignor's Interest
Nov 24, 2010
From: SAMSUNG ELECTRONICS CO., LTD.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 025419/0975 →
Assignment of Assignor's Interest
Nov 25, 2010
From: SAMSUNG ELECTRONICS CO., LTD.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 025423/0255 →
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Assignment of Assignor's Interest
Aug 16, 2013
From: UH, HYUNG-SOO; SONG, SANG-HO; KIM, KI-NAM
To: SAMSUNG ELECTRONICS CO., LTD.,
Reel/Frame 031025/0048 →
Corrective Assignment to Correct the Inventor Name Was Incorrectly Entered on Recordation Sheet. Previously Recorded on Reel 011420 Frame 0392. Assignor(S) Hereby Confirms the Correct Inventor's Name Is Hong-Il Yoon.
Aug 22, 2013
From: YOON, HONG-IL
To: SAMSUNG ELECTRONICS CO., LTD.,
Reel/Frame 031078/0865 →
Change of Name
Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
Change of Address
Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
Amended and Restated U.S. Patent Security Agreement (for Non-U.S. Grantors)
Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →