Recessed gate electrode MOS transistors having a substantially uniform channel length across a width of the recessed gate electrode and methods of forming same
View Patent ↗A transistor can include an integrated circuit substrate including spaced apart isolation regions therein and an active region therebetween. A recess is formed in the active region and extends between the spaced apart isolation regions and has a bottom and opposing side wall ends that are defined by facing portions of the spaced apart isolation regions. An electrically insulating layer is formed on the bottom of the recess. A conductive material is formed in the recess on the electrically insulating layer to provide a gate electrode.
1. A transistor comprising:
an integrated circuit substrate including spaced apart isolation regions therein and an active region therebetween;
a recess in the active region extending between the spaced apart isolation regions and having a bottom and opposing side wall ends defined by facing portions of the spaced apart isolation regions;
an electrically insulating layer on the bottom of the recess; and
a conductive material in the recess on the electrically insulating layer to provide a gate electrode.
2. A transistor according to claim 1 further comprising:
first and second source/drain regions in the active region on opposite sides of the gate electrode; and
a channel in the active region opposite the gate electrode between the first and second source/drain regions that extends along the recess.
3. A transistor according to claim 1 wherein the gate electrode directly contacts at least one of the opposing side wall ends of the recess.
4. A transistor according to claim 1 wherein the opposing side wall ends of the recess are free of the electrically insulating layer.
5. A transistor according to claim 1 wherein the bottom and one of the opposing side walls of the recess define an acute angle.
6. A transistor according to claim 1 , wherein:
a longitudinal side wall of the recess extends between the opposing side wall ends, substantially orthogonal to the bottom of the recess.
7. A transistor according to claim 1 wherein the bottom of the recess is above a bottom of at least one of the spaced apart isolation regions.
8. A transistor comprising a gate electrode embedded the recess having in an active region of a substrate, the recess having opposing side wall ends defined by facing portions of spaced apart isolation regions in the substrate, the gate electrode configured to control conduction of carriers through a channel in the active region opposite the gate electrode, wherein a length of the channel between a source region and a drain region is substantially uniform across an entire width of the channel.
9. A transistor according to claim 8 wherein the channel is only beneath a bottom of the gate electrode.
10. A transistor according to claim 8 further comprising:
an isolation region that defines one end of the width of the channel at the bottom of the gate electrode.
11. A method of forming a gate electrode of a transistor comprising:
forming a recess in an active region between spaced apart isolation regions of a substrate, the recess extending between the spaced apart isolation regions and having a bottom and opposing side wall ends defined by facing portions of the spaced apart isolation regions;
forming an electrically insulating layer on the bottom of the recess; and
forming a gate electrode in the recess on the electrically insulating layer.
12. A method according to claim 11 wherein the step of forming a recess comprises:
removing a first portion of the substrate between the spaced apart isolation regions to form a first portion of the recess wherein the opposing faces of the isolation regions are covered by remaining portions of the substrate; and
separately removing the remaining portions of the substrate to expose the opposing faces of the isolation regions.
13. A method according to claim 12 :
wherein the step of removing a first portion comprises etching the substrate to form the first portion of the recess; and
wherein the step of separately removing comprises isotropically etching the remaining portions to expose the opposing faces of the isolation regions.
14. A method according to claim 12 wherein the step of removing a first portion comprises etching the substrate to a level above a bottom of the isolation regions.
15. A method according to claim 14 wherein the level comprises about 100 nm to about 150 nm below a surface of the isolation regions.
16. A method according to claim 12 wherein the step of separately removing comprises isotropically etching the remaining portions further comprises etching a bottom surface of the recess to reduce a level of the bottom in a range between about 10 nm to about 50 nm.
17. A method according to claim 11 wherein the step of forming a recess comprises:
removing a first portion of the substrate between the spaced apart isolation regions to form a first portion of the recess wherein the opposing faces of the isolation regions are covered by remaining portions of the substrate;
oxidizing a surface of the remaining portions to form an oxidize surface of the remaining portions; and
removing the oxidized surface to expose the opposing faces of the isolation regions.
18. A method of forming a gate electrode of a transistor comprising:
etching an active region between spaced apart isolation regions of a substrate to form a recess extending between the spaced apart isolation regions and having a bottom and opposing side wall ends defined by remaining portions the substrate on opposing facing portions of the spaced apart isolation regions;
isotropically etching the remaining portions to expose the opposing facing portions of the spaced apart isolation regions to enlarge the recess so that the opposing side wall ends of the recess are defined by opposing facing portions of the spaced apart isolation regions;
forming an electrically insulating material on the bottom extending between the opposing facing portions of the spaced apart isolation regions; and
forming a conductive material in the recess on the electrically insulating layer to form a gate electrode in the recess.
19. A method according to claim 18 wherein the step of isotropically etching comprises removing all of the remaining portions from opposing facing portions of the spaced apart isolation regions so that the isolation regions are exposed.
20. A method according to claim 18 wherein the gate electrode controls conduction through a channel in the substrate that is only beneath the gate electrode.
21. A method according to claim 18 wherein the step of isotropically etching comprises isotropically etching using CF 4 +O 2 gas.
22. A method according to claim 18 wherein the step of etching an active region between spaced apart isolation regions of a substrate to form a recess comprises:
etching the active region between spaced apart isolation regions of a substrate to form a recess of a width that is less than or equal to a critical dimension of the gate electrode.