Semiconductor device having metal lines with slits
View Patent ↗A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.
1. A semiconductor device, comprising:
a semiconductor substrate;
an integrated circuit on the semiconductor substrate, the integrated circuit including a logic device having:
an N-channel MOS transistor having an N-type source region and an N-type drain region formed in the semiconductor substrate; and
a P-channel MOS transistor having a P-type source region and a P-type drain region formed in the semiconductor substrate;
an insulation layer covering the integrated circuit; and
a plurality of metal line patterns on the insulating layer, wherein:
first and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit,
at least one of the first and second metal line patterns is a ground line or a power supply line, and
the first metal line pattern is electrically connected to the N-type source region of the N-channel MOS transistor, and the second metal line pattern is electrically connected to the P-type source region of the P-channel MOS transistor.
2. The semiconductor device as claimed in claim 1 , wherein the integrated circuit further includes the SRAM device, and the SRAM device comprises a CMOS SRAM cell including a pair of driver transistors, a pair of load transistors and a pair of transfer transistors, and wherein the first metal line pattern is electrically connected to source regions of the pair of driver transistors and the second metal line pattern is electrically connected to source regions of the pair of load transistors.
3. The semiconductor device as claimed in claim 1 , wherein the integrated circuit further includes the flash memory device, and the flash memory device comprises a NAND string including a ground selection transistor, a plurality of cell transistors and a string selection transistor which are serially connected to one another, and wherein the first metal line pattern is electrically connected to a source region of the ground selection transistor.
4. The semiconductor device as claimed in claim 3 , wherein the NAND string corresponds to a lower NAND string, and the semiconductor device further comprises an upper NAND string stacked over the lower NAND string, wherein the first metal line pattern is electrically connected to the upper NAND string.