Semiconductor device having metal lines with slits
View Patent ↗A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.
1. A semiconductor device, comprising:
a semiconductor substrate;
an integrated circuit on the semiconductor substrate;
an insulation layer covering the integrated circuit;
a barrier layer covering the insulation layer; and
a plurality of metal line patterns on the barrier layer, wherein first and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit adjacent to the space.
2. The semiconductor device as claimed in claim 1 , further comprising an additional insulation layer between the insulation layer and the barrier layer.
3. The semiconductor device as claimed in claim 2 , further comprising a resistive layer between the additional insulation layer and the insulation layer.
4. The semiconductor device as claimed in claim 1 , wherein the slits are less than about 4 μm from the space.
5. The semiconductor device as claimed in claim 1 , wherein the space is about 1 μm.
6. The semiconductor device as claimed in claim 1 , wherein the space is about 1 μm.
7. The semiconductor device as claimed in claim 1 , wherein the slits have a width greater than about 1 μm.
8. The semiconductor device as claimed in claim 1 , wherein the first and second metal line patterns have a width greater than about 30 μm.
9. The semiconductor device as claimed in claim 1 , wherein each metal line pattern of the plurality of metal line patterns having a width greater than about 30 μm and is adjacent to another metal line pattern of the plurality of metal line patterns having a width greater than about 30 μm has at least one slit.
10. A semiconductor device, comprising:
a semiconductor substrate;
an integrated circuit on the semiconductor substrate;
an insulation layer covering the integrated circuit;
a plurality of metal line patterns over the insulation layer, wherein first and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit adjacent to the space; and
a barrier layer between the plurality of metal line patterns and the insulation layer.
11. The semiconductor device as claimed in claim 10 , further comprising an additional insulation layer between the insulation layer and the barrier layer.
12. The semiconductor device as claimed in claim 11 , further comprising a resistive layer between the additional insulation layer and the insulation layer.
13. The semiconductor device as claimed in claim 10 , wherein the slits are less than about 4 μm from the space.
14. The semiconductor device as claimed in claim 10 , wherein the space is about 10 μm.
15. The semiconductor device as claimed in claim 10 , wherein the space is about 1 μm.
16. The semiconductor device as claimed in claim 10 , wherein the slits have a width greater than about 1 μm.
17. The semiconductor device as claimed in claim 10 , wherein the first and second metal line patterns have a width greater than about 30 μm.
18. The semiconductor device as claimed in claim 10 , wherein each metal line pattern of the plurality of metal line patterns having a width greater than about 30 μm and adjacent to another metal line pattern of the plurality of metal line patterns having a width greater than about 30 μm has at least one slit.
19. A semiconductor device, comprising:
a semiconductor substrate;
an integrated circuit on the semiconductor substrate;
a first insulation layer covering the integrated circuit;
a second insulation layer covering the first insulation layer; and
a plurality of metal line patterns on the second insulation layer, wherein first and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit adjacent to the space.
20. The semiconductor device as claimed in claim 19 , further comprising a barrier layer between the plurality of metal line patterns and the second insulation layer.
21. The semiconductor device as claimed in claim 20 , further comprising a resistive layer between the first insulation layer and the second insulation layer.
22. The semiconductor device as claimed in claim 19 , wherein the slits are less than about 4 μm from the space.
23. The semiconductor device as claimed in claim 19 , wherein the space is about 10 μm.
24. The semiconductor device as claimed in claim 19 , wherein the space is about 1 μm.
25. The semiconductor device as claimed in claim 19 , wherein the slits have a width greater than about 1 μm.
26. The semiconductor device as claimed in claim 19 , wherein the first and second metal line patterns have a width greater than about 30 μm.
27. The semiconductor device as claimed in claim 19 , wherein each metal line pattern of the plurality of metal line patterns having a width greater than about 30 μm and adjacent to another metal line pattern of the plurality of metal line patterns having a width greater than about 30 μm has at least one slit.