Method and apparatus for selecting an encryption integrated circuit operating mode
View Patent ↗A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.
1. An apparatus for processing or storing secure data comprising:
a secure port for transmitting and receiving secure data;
a test port for transmitting and receiving test data; and
a test mode entry circuit that causes entry of the apparatus into a test mode, the test mode entry circuit operable for a predetermined time period, the test mode entry circuit being coupled to the secure port, the test mode entry circuit causing entry of the apparatus into a work mode when secure data is applied to the secure port.
2. The apparatus of claim 1 , wherein the entry into the work mode disables re-entry of the apparatus to the test mode.
3. The apparatus of claim 1 , wherein the predetermined time period commences approximately coincident to when power is applied to the apparatus.
4. An apparatus for processing or storing secure data, comprising:
a secure port for transmitting and receiving secure data;
a test port for transmitting and receiving test data;
a test mode entry circuit that causes entry of the apparatus into a test mode, the test mode entry circuit operable for a predetermined time period; and
test circuitry coupled to the test mode entry circuit, the test circuitry performing diagnostic functions while the apparatus is in the test mode.
5. An apparatus for processing or storing secure data, comprising:
a secure port for transmitting and receiving secure data;
a test port for transmitting and receiving test data; and
a test mode entry circuit that causes entry of the apparatus into a test mode, the test mode entry circuit operable for a predetermined time period, the test mode entry circuit being coupled to the test port, entry into the test mode being dependent on test data received through the test port within the predetermined time period, the test data comprising one or more electrical signals received through the test port and at least one of the electrical signals being an out of static super voltage.
6. An apparatus for processing or storing secure data, comprising:
a secure port for transmitting and receiving secure data;
a test port for transmitting and receiving test data; and
a test mode entry circuit that causes entry of the apparatus into a test mode, the test mode entry circuit operable for a predetermined time period, the test mode entry circuit causing the apparatus to enter a work mode if no test data is received within the predetermined time period.
7. An apparatus for processing or storing secure data, comprising:
a secure port for transmitting and receiving secure data;
a test port for transmitting and receiving test data;
a test mode entry circuit that causes entry of the apparatus into a test mode, the test mode entry circuit operable for a predetermined time period,
non-volatile memory for storing the secure data; and
a memory erasing circuit for erasing the secure data stored in the non-volatile memory upon entry of the apparatus into the test mode.