Low leakage and data retention circuitry
View Patent ↗An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
1. An integrated circuit comprising:
a plurality of power islands having associated power consumptions, each of the power islands including circuitries and sleep transistors in coupled relation with the circuitries, and the sleep transistors being included within the integrated circuit to facilitate reduction of power consumed by the circuitries;
a power island manager configured to dynamically change the power consumptions based on needs and operation of the integrated circuit, the power island manager in communication with at least one of the power islands; and
an adaptive leakage controller configured to control change of a variable voltage to be applied to the sleep transistors, and the power island manager configured to generate the variable voltage based on a control signal received from the adaptive leakage controller.
2. The integrated circuit as claimed in claim 1 wherein the at least one of the power islands can be put to sleep and taken out of sleep at different times.
3. The integrated circuit as claimed in claim 2 wherein the power island manager includes a state machine to control when the at least one of the power islands is put to sleep and when the at least one of the power islands is taken out of sleep.
4. The integrated circuit as claimed in claim 1 wherein the power islands are delineated based on functional intellectual property units of the integrated circuit.
5. The integrated circuit as claimed in claim 1 wherein the power islands are delineated by memory, logic and third party intellectual property.
6. The integrated circuit as claimed in claim 1 wherein the variable voltage is an optimum voltage.
7. The integrated circuit as claimed in claim 6 wherein the optimum voltage is dependent upon both process variation and temperature variation.
8. The integrated circuit as claimed in claim 6 wherein the optimum voltage is generated by a sleep generator within the power island manager.
9. The integrated circuit as claimed in claim 8 wherein the sleep generator comprises a charge pump.
10. The integrated circuit as claimed in claim 1 wherein the variable voltage is generated by a sleep generator within the power island manager.
11. The integrated circuit as claimed in claim 10 wherein the sleep generator comprises a charge pump.
12. The integrated circuit as claimed in claim 11 wherein the control signal is a digital signal.
13. The integrated circuit as claimed in claim 1 further comprising a central processing unit separate from and in communication with the power island manager.
14. The integrated circuit as claimed in claim 13 further comprising another power island manager, the central processing unit separate from and in communication with the another power island manager.
15. An integrated circuit comprising:
a plurality of power islands having associated power consumptions, and the power consumptions being dynamically changeable based on needs and operation of the integrated circuit, and each of the power islands including circuitries and sleep transistors in coupled relation with the circuitries, and the sleep transistors being included within the integrated circuit to facilitate reduction of power consumed by the circuitries;
a sleep generator including a charge pump to generate a variable voltage to be applied to the sleep transistors; and
an adaptive leakage controller configured to control change of the variable voltage by providing a digital control signal to the sleep generator.
16. The integrated circuit as claimed in claim 15 wherein the power islands are delineated based on functional intellectual property units of the integrated circuit.
17. The integrated circuit as claimed in claim 15 wherein the power islands are delineated by memory, logic and third party intellectual property.
18. The integrated circuit as claimed in claim 15 wherein the variable voltage is an optimum voltage.
19. The integrated circuit as claimed in claim 18 wherein the optimum voltage is dependent upon both process variation and temperature variation.