Word line driver in a hierarchical NOR flash memory
View Patent ↗A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
1. A memory device of the non-volatile type comprising:
a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line being coupled to the main word line by a respective two-transistor-only local word line driver circuit, each of the two-transistor-only local word line driver circuits having a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal;
wherein during a programming operation of a selected sector the first biasing terminal is set at a negative voltage;
wherein during the programming operation of the selected sector the transistors of the two-transistor-only local word line driver circuits of the selected sector are biased such that de-selected local word lines from the selected sector are biased at said negative voltage; and
wherein the transistors are biased such that during an erase operation, local word lines of a non-selected sector are biased at a positive voltage.
2. The memory device of claim 1 , wherein the first biasing terminal is common to the two-transistor-only local word line drivers in each of the sectors.
3. The memory device of claim 1 , wherein the second MOS transistor is an NMOS transistor.
4. The memory device of claim 3 , wherein the NMOS transistor is a triple-well transistor.
5. The memory device of claim 3 , wherein the first MOS transistors is a PMOS transistor.
6. The memory device of claim 3 , wherein the first MOS transistor is an NMOS transistor.
7. The memory device of claim 6 , wherein the NMOS transistors are triple-well transistors.
8. The memory device of claim 1 , wherein the first biasing terminal is set to a ground potential during an erase operation.
9. The memory device of claim 1 , wherein the memory device is a SPI serial flash memory device.
10. The memory device of claim 1 , wherein a body terminal of the second MOS transistor is electrically coupled to the first biasing terminal.
11. The memory device of claim 1 , wherein the memory array is a serial flash array of NOR type memory cells organized in a plurality of blocks and each block comprises a plurality of the sectors.
12. A two-transistor-only word line driver circuit for a hierarchical memory comprising:
only two MOS transistors, a first MOS transistor of the only two MOS transistors coupling a main word line to a one local word line of a plurality of local word lines, the first MOS transistor being selectively biased to pass a first voltage from the main word line to the one local word line, and a second MOS transistor of the only two MOS transistors coupling the one local word line to a biasing terminal, the second MOS transistor being selectively biased to pass a second voltage from the biasing terminal to the one local word line;
wherein during a programming operation the biasing terminal is set at a negative voltage;
wherein during the programming operation of a selected sector the transistors of the two-transistor-only word line driver circuits of the selected sector are biased such that de-selected local word lines from the selected sector are biased at said negative voltage; and
wherein the transistors are biased such that during an erase operation, local word lines of a non-selected sector are biased at a positive voltage.
13. The two-transistor-only word line driver circuit of claim 12 , wherein the first and second MOS transistors are NMOS transistors.
14. The two-transistor-only word line driver circuit of claim 13 , wherein the NMOS transistors are triple-well transistors.
15. The two-transistor-only word line driver circuit of claim 14 , wherein the biasing terminal is set to a ground potential during an erase operation.
16. The two-transistor-only word line driver circuit of claim 12 , wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor.
17. The two-transistor-only word line driver circuit of claim 12 , wherein a body terminal of the second MOS transistor is electrically coupled to the biasing terminal.