Voltage level shifter and buffer using same
View Patent ↗A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.
1. A circuit comprising:
an input circuit including a pair of input field effect transistors (FETs) of a first polarity,
said input circuit receiving a differential input signal and connected between a first supply voltage and a pair of output nodes,
said differential input signal varying between an input high level and an input low level, said varying dependent upon a bias voltage; and
a reference voltage generator for receiving said bias voltage and generating a variable reference voltage;
a load chain circuit including a pair of cross-coupled load chain FETs of a second polarity,
respective gates of said pair of cross-coupled load chain FETs connected to respective nodes of said pair of output nodes,
said load chain circuit receiving said variable reference voltage and including a pair of regulated current sources,
said pair of regulated current sources regulated by said variable reference voltage thereby coordinating a strength of said current sources with a strength of said input circuit,
a pair of feedback elements, each feedback element of said pair of feedback elements associated with a respective one of said pair of cross-coupled load chain FETs, said each feedback element configured to:
produce a feedback signal indicative of a state of a respective one of said pair of output nodes; and
provide said feedback signal to a respective one of said pair of regulated current sources; and
said load chain circuit connected directly between a second supply voltage and said pair of output nodes such that an output signal at said output nodes varies between an output high level and an output low level.
2. The circuit as claimed in claim 1 further comprising:
a bias voltage generator for:
providing said bias voltage to said reference voltage generator; and
providing said bias voltage to a voltage controlled delay line.
3. The circuit as claimed in claim 2 wherein said voltage controlled delay line comprises:
a plurality of delay elements serially connected by a differential pair of delay lines.
4. The circuit as claimed in claim 2 wherein a delay of at least one of said plurality of delay elements is controlled by said bias voltage.
5. The circuit as claimed in claim 2 wherein said differential input signal is provided from a tapping point of said voltage controlled delay line.
6. A method comprising:
at an input circuit including a pair of input field effect transistors (FETs) of a first polarity, said input circuit connected between a first supply voltage and a pair of output nodes:
receiving a differential input signal, said differential input signal varying between an input high level and an input low level, said varying dependent upon a bias voltage; and
at a reference voltage generator:
receiving said bias voltage; and
generating a variable reference voltage;
at a load chain circuit including a pair of cross-coupled load chain FETs of a second polarity, respective gates of said pair of cross-coupled load chain FETs connected to respective nodes of said pair of output nodes, said load chain circuit including a pair of regulated current sources regulated by said variable reference voltage thereby coordinating a strength of said current sources with a strength of said input circuit, said load chain circuit connected directly between a second supply voltage and said pair of output nodes such that an output signal at said output nodes varies between an output high level and an output low level:
receiving said variable reference voltage;
receiving a feedback signal; and
producing a current based on said reference voltage and said feedback signal.
7. The method as claimed in claim 6 further comprising:
at a bias voltage generator:
providing said bias voltage to said reference voltage generator; and
providing said bias voltage to a voltage controlled delay line.
8. The method as claimed in claim 7 further comprising controlling, by said bias voltage, a delay of at least one of said plurality of delay elements.
9. The method as claimed in claim 7 further comprising providing said differential input signal from a tapping point of said voltage controlled delay line.