Nonvolatile memory having non-power of two memory capacity
View Patent ↗A nonvolatile memory having a non-power of two memory capacity is provided. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device.
1. A nonvolatile memory device comprising:
a plurality of planes totaling three, five, six or seven in number, and said plurality of planes each comprising a data section, a spare fields section and a redundant column or columns section, and said plurality of planes each including a plurality of blocks with each said blocks divided into a number of pages and each said blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension by a second number of memory cells for storing data, the nonvolatile memory device having a non-power of two capacity;
a plurality of high voltage generators totaling less in number than the number of planes, a first of the plurality of high voltage generators for providing high voltages in connection with operations that occur in a first of the plurality of planes, a second of the plurality of high voltage generators for providing high voltages in connection with operations that occur in a second of the plurality of planes; and
a plurality of row decoders in each said plurality of planes, and an at least substantially one-to-one relationship existing, in the nonvolatile memory device, for number of row decoders to number of pages, and each said row decoders configured to facilitate a read operation on an associated page of the nonvolatile memory device.
2. The nonvolatile memory device as claimed in claim 1 wherein said plurality of row decoders is a non-power of two number of row decoders.
3. The nonvolatile memory device as claimed in claim 1 wherein a third of the plurality of planes is configured to receive high voltages from the first of the plurality of high voltage generators.
4. The nonvolatile memory device as claimed in claim 1 wherein the nonvolatile memory device is a flash memory device.
5. The nonvolatile memory device as claimed in claim 1 wherein the nonvolatile memory device is a NAND flash memory device.
6. A memory system comprising:
the nonvolatile memory device as claimed in claim 1 ; and
a controller in communication with said nonvolatile memory device, said controller including storage and a management module, said storage storing a map table, said management module configured to access the map table to carry out translation of logical addresses to physical addresses, and invalid physical addresses attributable to the non-power of two capacity of said nonvolatile memory device being mapped out in the map table.
7. The memory system as claimed in claim 6 wherein said nonvolatile memory device has a non-power of two number of row decoders.
8. The memory system as claimed in claim 6 wherein said nonvolatile memory device is a NAND flash memory device, and said management module includes an allocator for handling translation of logical addresses to physical addresses in accordance with NAND Flash Translation Layer (NFTL).
9. The memory system as claimed in claim 6 wherein said nonvolatile memory device is a flash memory device.
10. The memory system as claimed in claim 6 wherein said nonvolatile memory device is a NAND flash memory device.
11. The memory system as claimed in claim 6 wherein said nonvolatile memory device fits within a 48-pin TSOP-1 package.
12. The nonvolatile memory device as claimed in claim 1 wherein said plurality of high voltage generators comprise a plurality of charge pumps.
13. The nonvolatile memory device as claimed in claim 1 wherein the nonvolatile memory device fits within a 48-pin TSOP-1 package.