Semiconductor device with configurable through-silicon vias
View Patent ↗Disclosed is a semiconductor device that comprises a plurality of through-silicon vias (TSVs), a signal line and a selective connector for causing the signal line to be either electrically connected to one of the TSVs or electrically isolated from all of the TSVs, based on a control signal.
1. A semiconductor device, comprising:
a plurality of through-silicon vias (TSVs);
a signal line; and
a selective connector for causing the signal line to be either electrically connected to one of the TSVs or electrically isolated from all of the TSVs, based on a control signal.
2. The semiconductor device defined in claim 1 , wherein the selective connector is for causing the signal line to be electrically connected to a particular one of the TSVs when the control signal has a first predetermined value and for causing the signal line to be electrically isolated from all of the TSVs when the control signal has a second predetermined value.
3. The semiconductor device defined in claim 1 , wherein each of the TSVs occupies a respective position relative to the selective connector, wherein the control signal encodes a desired output position, and wherein the selective connector is for causing the signal line to be electrically connected to a particular one of the TSVs whose respective position relative to the selective connector is the desired output position.
4. The semiconductor device defined in claim 1 , wherein the selective connector comprises a transmission gate.
5. The semiconductor device defined in claim 1 , wherein the selective connector comprises a demultiplexer configured to acquire a high-impedance output state when the control signal has a predetermined value.
6. The semiconductor device defined in claim 1 , wherein the selective connector comprises a demultiplexer in series with a transmission gate.
7. The semiconductor device defined in claim 6 , wherein each of the TSVs occupies a respective position relative to the demultiplexer, wherein the control signal encodes a desired output position, and wherein the demultiplexer is configured to cause an output of the transmission gate to be electrically connected to a particular one of the TSVs whose respective position relative to the demultiplexer is the desired output position.
8. The semiconductor device defined in claim 1 , wherein the signal line is one of a plurality of signal lines and wherein the selective connector is one of a plurality of selective connectors, each for causing a respective one of the signal lines to be either electrically connected to one of the TSVs in a respective subset of the TSVs corresponding to that signal line or electrically isolated from all of the TSVs, based on a respective control signal.
9. The semiconductor device defined in claim 8 , wherein the respective subset of TSVs corresponding to each of the signal lines includes at least two TSVs on the semiconductor device.
10. The semiconductor device defined in claim 9 , wherein at least some of the TSVs belong to more than one of the subsets of TSVs.
11. The semiconductor device defined in claim 10 , wherein the subsets of TSVs together include more TSVs than there are signal lines in the plurality of signal lines.
12. The semiconductor device defined in claim 1 , further comprising:
a controller for generating the control signal.
13. A semiconductor apparatus, comprising:
a plurality of stacked semiconductor dies, each semiconductor die comprising:
a plurality of through-silicon vias (TSVs);
a plurality of signal lines, each corresponding to a respective subset of the TSVs; and
a plurality of selective connectors, each for causing a respective one of the signal lines to be either electrically connected to one of the TSVs in the respective subset of the TSVs or electrically isolated from all of the TSVs, based on a respective control signal.
14. The semiconductor apparatus defined in claim 13 , wherein each selective connector is for causing the respective one of the signal lines to be electrically connected to a particular one of the TSVs when the respective control signal has a first predetermined value and for causing the respective one of the signal lines to be electrically isolated from all of the TSVs when the respective control signal has a second predetermined value.
15. The semiconductor apparatus defined in claim 13 , wherein for each selective connector: each of the TSVs in the respective subset of TSVs occupies a respective position relative to the selective connector, the respective control signal encodes a desired output position, and the selective connector is for causing the respective one of the signal lines to be electrically connected to a particular one of the TSVs in the respective subset of TSVs whose respective position relative to the selective connector is the desired output position.
16. The semiconductor apparatus defined in claim 13 , wherein each selective connector comprises a transmission gate.
17. The semiconductor apparatus defined in claim 13 , wherein each selective connector comprises a demultiplexer capable of acquiring a high-impedance output state.
18. The semiconductor apparatus defined in claim 13 , wherein each selective connector comprises a demultiplexer in series with a transmission gate.
19. The semiconductor apparatus defined in claim 18 , wherein for each selective connector: each of the TSVs in the respective subset of TSVs occupies a respective position relative to the demultiplexer, the respective control signal encodes a desired output position, and the demultiplexer is configured to cause an output of the transmission gate to be electrically connected to a particular one of the TSVs whose respective position relative to the demultiplexer is the desired output position.
20. The stacked semiconductor apparatus defined in claim 13 , wherein the respective subset of TSVs corresponding to each of the signal lines on a particular one of the semiconductor dies includes at least two TSVs on the particular semiconductor die.
21. The stacked semiconductor apparatus defined in claim 20 , wherein at least some of the TSVs on the particular semiconductor die belong to more than one of the subsets of TSVs on the particular semiconductor die.
22. The stacked semiconductor apparatus defined in claim 21 , wherein the subsets of TSVs on the particular die together include more TSVs than there are signal lines in the plurality of signal lines on the particular semiconductor die.
23. The stacked semiconductor apparatus defined in claim 13 , further comprising a plurality of bonding pads for electrically connecting corresponding TSVs on adjacently stacked ones of the semiconductor dies to one another.
24. The stacked semiconductor apparatus defined in claim 13 , further comprising a substrate and a plurality of bonding pads for electrically connecting the TSVs on a given one of the semiconductor dies to corresponding signal lines of the substrate.
25. The stacked semiconductor apparatus defined in claim 13 , wherein the TSVs on a particular one of the semiconductor dies are concentrated within at least one zone of the particular semiconductor die, the at least one zone occupying no more than 15% of the surface area of the particular semiconductor die.
26. The stacked semiconductor apparatus defined in claim 13 , wherein the TSVs on a particular one of the semiconductor dies are concentrated within a plurality of zones of the particular semiconductor die, at least two of said zones being separated by functional circuitry on the particular semiconductor die.
27. A method of configuring a semiconductor device that comprises a plurality of through-silicon vias (TSVs) and a signal line, the method comprising:
determining a connectivity requirement for the signal line relative to the TSVs;
providing a control signal to a selective connector on the semiconductor device, the control signal having a value that depends on an outcome of said determining;
said selective connector causing the signal line to be either electrically connected to one of the TSVs or electrically isolated from all of the TSVs, in dependence upon the value of the control signal.
28. A semiconductor apparatus, comprising:
a plurality of through-silicon vias (TSVs);
a plurality of signal lines; and
a first connector having been previously configured to electrically connect a first one of the signal lines to one of the TSVs; and
a second connector having been previously configured to electrically isolate the second one of the signal lines from all of the TSVs.
29. The semiconductor apparatus defined in claim 28 , further comprising a first semiconductor die and a second semiconductor die, wherein first ones of the TSVs are located on the first semiconductor die, wherein second ones of the TSVs are located on the second semiconductor die and electrically connected to respective ones of the first TSVs, wherein the first signal line and the first connector are located on the first semiconductor die, and wherein the second signal line and the second connector are located on the second semiconductor die.
30. The semiconductor apparatus defined in claim 29 , further comprising a plurality of bonding pads for connecting the respective ones of the first TSVs to the respective ones of the second TSVs.
31. The semiconductor apparatus defined in claim 29 , further comprising a substrate and a plurality of bonding pads for electrically connecting the TSVs on the first semiconductor die to corresponding signal lines of the substrate.
32. The semiconductor apparatus defined in claim 28 , further comprising a plurality of semiconductor dies, wherein the TSVs, the signal lines, the first connector and the second connector are all located on the same semiconductor die.
33. The semiconductor apparatus defined in claim 32 , further comprising a substrate and a plurality of bonding pads for electrically connecting the TSVs on said same semiconductor die to corresponding signal lines of the substrate.