Intialization circuit for delay locked loop
View Patent ↗An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.
1. A delay locked loop comprising:
a delay circuit which provides a delay to a reference clock to generate a feedback clock, the delay circuit having a delay range;
a phase detector which compares phase of the reference clock and the feedback clock to change the delay of the delay circuit; and
an initialization circuit which, once the delay locked loop is reset:
i) enables the phase detector to initially change the delay in a direction away from a first end of the delay range; and
ii) enables a change in the delay in an opposite direction toward the first end only after a number of clock cycles later.
2. The delay locked loop of claim 1 wherein the number of clock cycles is an integer number of clock cycles greater than zero.
3. The delay locked loop of claim 1 wherein the delay circuit comprises a voltage controlled delay line.
4. The delay locked loop of claim 1 wherein the delay circuit comprises a tapped delay line.
5. The delay locked loop of claim 1 wherein the delay circuit comprises a digital delay line.
6. The delay locked loop of claim 1 wherein the first end of the delay range is a minimum delay and the direction away from the first end increases the delay and the opposite direction towards the first end decreases the delay.
7. The delay locked loop of claim 1 wherein when the phase detector is initially changing the delay it is only increasing the delay.
8. The delay locked loop of claim 1 wherein the initialization circuit comprises a first latch responsive to the reference clock and a second latch responsive to the feedback clock.
9. The delay locked loop of claim 8 wherein the first latch is configured to detect a first edge of the reference clock, and the second latch is configured to detect an edge of the feedback clock after the first edge of the reference clock has been detected by the first latch.
10. The delay locked loop of claim 9 wherein the input of the second latch is coupled to the output of the first latch.
11. The delay locked loop of claim 9 wherein the first edge of the reference clock is a rising edge and the edge of the feedback clock is a rising edge.
12. The delay locked loop of claim 9 wherein the initialization circuit further comprises a third latch responsive to the reference clock and a fourth latch responsive to the feedback clock.
13. The delay locked loop of claim 12 wherein the third latch is configured to detect a next edge of the reference clock and the fourth latch is configured to detect a next edge of the feedback clock to delay the enabling of change in the delay in the opposite direction for at least one feedback clock period.
14. The delay locked loop of claim 13 wherein the input of the third latch is coupled to the output of the first latch, and the input of the fourth latch is coupled to the output of the third latch.
15. The delay locked loop of claim 1 wherein the phase detector comprises: a latch responsive to the reference clock to generate a first phase control signal; and another latch responsive to the feedback clock to generate a second phase control signal.
16. The delay locked loop of claim 1 , further comprising a reset circuit controlling the reset of the delay locked loop in response to a reset signal, the initialization circuit resetting in response to the reset signal.
17. The delay locked loop of claim 1 , further comprising a reset circuit controlling the reset of the delay locked loop in response to a reset signal, the phase detector resetting in response to the reset signal.
18. The delay locked loop of claim 1 wherein the initialization circuit further comprises an input to receive a reset signal; and wherein the phase detector further comprises an input to receive the reset signal.
19. The delay locked loop of claim 1 wherein the reset signal is an active-low signal.
20. A delay locked loop comprising:
a delay circuit which provides a delay to a reference clock to generate a feedback clock, the delay circuit having a delay range;
a phase detector which compares phase of the reference clock and the feedback clock to change the delay of the delay circuit; and
an initialization circuit which, once the delay locked loop is reset:
i) enables the phase detector to initially change the delay in a direction away from a first end of the delay range; and
ii) enables a change in the delay in an opposite direction toward the first end only after a predetermined number of clock cycles later.
21. The delay locked loop of claim 20 wherein the number of clock cycles is an integer number of clock cycles greater than zero.
22. The delay locked loop of claim 20 wherein the delay circuit comprises a voltage controlled delay line.
23. The delay locked loop of claim 20 wherein the delay circuit comprises a tapped delay line.
24. The delay locked loop of claim 20 wherein the delay circuit comprises a digital delay line.
25. The delay locked loop of claim 20 wherein the first end of the delay range is a minimum delay and the direction away from the first end increases the delay and the opposite direction towards the first end decreases the delay.
26. The delay locked loop of claim 20 wherein when the phase detector is initially changing the delay it is only increasing the delay.
27. The delay locked loop of claim 20 wherein the initialization circuit comprises a first latch responsive to the reference clock and a second latch responsive to the feedback clock.
28. The delay locked loop of claim 27 wherein the first latch is configured to detect a first edge of the reference clock, and the second latch is configured to detect an edge of the feedback clock after the first edge of the reference clock has been detected by the first latch.
29. The delay locked loop of claim 28 wherein the input of the second latch is coupled to the output of the first latch.
30. The delay locked loop of claim 28 wherein the first edge of the reference clock is a rising edge and the edge of the feedback clock is a rising edge.
31. The delay locked loop of claim 28 wherein the initialization circuit further comprises a third latch responsive to the reference clock and a fourth latch responsive to the feedback clock.
32. The delay locked loop of claim 31 wherein the third latch is configured to detect a next edge of the reference clock and the fourth latch is configured to detect a next edge of the feedback clock to delay the enabling of change in the delay in the opposite direction for at least one feedback clock period.
33. The delay locked loop of claim 32 wherein the input of the third latch is coupled to the output of the first latch, and the input of the fourth latch is coupled to the output of the third latch.
34. The delay locked loop of claim 20 wherein the phase detector comprises: a latch responsive to the reference clock to generate a first phase control signal; and another latch responsive to the feedback clock to generate a second phase control signal.
35. The delay locked loop of claim 20 , further comprising a reset circuit controlling the reset of the delay locked loop in response to a reset signal, the initialization circuit resetting in response to the reset signal.
36. The delay locked loop of claim 20 , further comprising a reset circuit controlling the reset of the delay locked loop in response to a reset signal, the phase detector resetting in response to the reset signal.
37. The delay locked loop of claim 20 wherein the initialization circuit further comprises an input to receive a reset signal; and wherein the phase detector further comprises an input to receive the reset signal.
38. The delay locked loop of claim 20 wherein the reset signal is an active-low signal.