Delay locked loop circuit
View Patent ↗The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off.
1. A method for adjusting the phase of a locked loop output signal with respect to a reference input signal comprising:
outputting a locked loop output signal from a delay circuit;
comparing the locked loop output signal and a reference input signal in a phase comparator to determine a phase difference;
activating at least one of an up control signal and a down control signal for a period of time based on the phase difference;
providing a source current to an integrating capacitor when the up control signal is activated;
providing a sink current to the integrating capacitor when the down control signal is activated, the sink current having a magnitude different from the magnitude of the source current;
adjusting a delay of the delay circuit based on a voltage on the integrating capacitor;
and
adjusting magnitudes of the source current and the sink current.
2. The method of claim 1 , wherein the locked loop is a delay locked loop.
3. The method of claim 1 , wherein the locked loop is a phase locked loop.
4. The method of claim 1 , wherein the reference input signal is a reference input clock signal and the locked loop output signal is a locked loop output clock signal.
5. The method of claim 1 , wherein the source current is a programmable source current.
6. The method of claim 5 , wherein the source current is provided by a plurality of current sources.
7. The method of claim 6 , wherein the source current is provided by a plurality of identical current sources.
8. The method of claim 6 , wherein the plurality of current sources are enabled by respective enable signals.
9. The method of claim 8 , wherein the respective enable signals are provided by registers.
10. The method of claim 1 , wherein the sink current is a programmable sink current.
11. The method of claim 10 , wherein the sink current is provided by a plurality of current sources.
12. The method of claim 11 , wherein the sink current is provided by a plurality of identical current sources.
13. The method of claim 11 , wherein the plurality of current sources are enabled by respective enable signals.
14. The method of claim 13 , wherein the respective enable signals are provided by registers.
15. A method for adjusting the phase of a locked loop output signal with respect to a reference input signal comprising:
outputting a locked loop output signal from an adjustable delay circuit;
comparing the locked loop output signal and a reference input signal in a phase comparator to determine a phase difference;
activating at least one of an up control signal and a down control signal for a period of time based on the phase difference;
providing a source current to an integrating capacitor when the up control signal is activated, the source current having an adjustable magnitude;
providing a sink current to the integrating capacitor when the down control signal is activated, the sink current having an adjustable magnitude, the magnitude of the sink current being adjustable independently of the magnitude of the source current; and
adjusting a delay of the adjustable delay circuit based on a voltage on the integrating capacitor; and
adjusting magnitudes of the source current and the sink current.
16. The method of claim 15 , wherein the locked loop is a delay locked loop.
17. The method of claim 15 , wherein the locked loop is a phase locked loop.
18. The method of claim 15 , wherein the source current is provided by a plurality of current sources.
19. The method of claim 18 , wherein the source current is provided by a plurality of identical current sources.
20. The method of claim 18 , wherein the plurality of current sources are enabled by respective enable signals.
21. The method of claim 15 , wherein the sink current is provided by a plurality of current sources.
22. The method of claim 21 , wherein the sink current is provided by a plurality of identical current sources.
23. The method of claim 21 , wherein the plurality of current sources are enabled by respective enable signals.
24. The method of claim 15 , wherein the delay of the adjustable delay circuit is based on the voltage on the integrating capacitor according to the formula:
Phase Shift=180* I N /( I M +I N )
where I M is a magnitude of the source current to the integrating capacitor and I N is a magnitude of the sink current to the integrating capacitor.
25. The method of claim 15 , wherein:
the source current is provided by a plurality of identical current sources enabled by respective source current enable signals;
the sink current is provided by a plurality of identical current sinks enabled by respective sink current enable signals; and
the delay of the adjustable delay circuit is based on the voltage on the integrating capacitor according to the formula:
Phase Shift=180*( N+ 1)/( M+N+ 2)
where M is a number of enabled current sources; and N is a number of enabled current sinks.