Flash memory device with improved programming performance
View Patent ↗A selected word line that is coupled to a cell to be programmed is biased during a program operation. The unselected word lines are biased with a negative potential to reduce the cell leakage at programming bit line potential. A programming pulse is applied to the bit line coupled to the cell to be programmed. During verification, the unselected word lines are biased back to ground potential.
1. A method for programming a memory device comprising a memory array having memory cells coupled to bit lines and word lines, the method comprising:
pulsing a selected bit line coupled to selected memory cells with a programming pulse having a first predetermined voltage;
biasing a selected word line coupled to the selected memory cells to a second predetermined voltage;
biasing unselected word lines coupled to unselected memory cells to a predetermined negative voltage;
performing a verify operation on the selected memory cells, the verify operation comprising:
biasing the selected bit line to a bit line verify voltage;
biasing the selected wordline to a wordline read voltage;
biasing the unselected wordlines to ground potential;
verifying a state of each of the selected memory cells; and
repeating programming attempts in response to a failure in verifying the state of at least one of the selected memory cells.
2. The method of claim 1 wherein a programming counter is incremented for each programming attempt.
3. The method of claim 2 wherein a programming error is indicated if the programming counter reaches a maximum number of programming attempts to be performed.
4. The method of claim 1 wherein the first predetermined voltage is in a range of 3 to 6V.
5. The method of claim 1 wherein the second predetermined voltage is in a range of 6 to 12V.
6. The method of claim 1 wherein the predetermined negative voltage is in the range of −0.1 to −8V.
7. The method of claim 1 wherein the bit line verify voltage is in the range of 0.2 to 1.2V.
8. The method of claim 1 wherein the wordline read voltage is in the range of 4 to 8V.
9. A memory device comprising:
a memory array having memory cells coupled to bit lines and word lines;
memory control circuitry, wherein the memory control circuitry is adapted to pulse a selected bit line coupled to selected memory cells with a programming pulse having a first predetermined voltage, bias a selected word line coupled to the selected memory cells to a second predetermined voltage, bias unselected word lines coupled to unselected memory cells to a predetermined negative voltage; and wherein the memory control circuitry is further adapted to bias the selected bit line to a bit line verify voltage, bias the selected wordline to a wordline read voltage, bias the unselected wordlines to ground potential, verify a state of each of the selected memory cells and repeat programming attempts in response to a failure in verifying the state of at least one of the selected memory cells.
10. The memory device of claim 9 wherein the memory control circuitry is a state machine.
11. The memory device of claim 9 wherein the memory cells are flash memory cells.
12. The memory device of claim 9 wherein the memory cells are coupled in a NOR type arrangement.
13. The memory device of claim 9 wherein the memory cells are coupled in a NAND type arrangement.
14. An electronic system comprising:
a processor for generating memory control signals; and
a memory device, coupled to receive the memory control signals, the memory device comprising:
a memory array having memory cells coupled to bit lines and word lines;
memory control circuitry, wherein the memory control circuitry is adapted to pulse a selected bit line coupled to selected memory cells with a programming pulse having a first predetermined voltage, bias a selected word line coupled to the selected memory cells to a second predetermined voltage, bias unselected word lines coupled to unselected memory cells to a predetermined negative voltage; and wherein the memory control circuitry is further adapted to bias the selected bit line to a bit line verify voltage, bias the selected wordline to a wordline read voltage, bias the unselected wordlines to ground potential, verify a state of each of the selected memory cells and repeat programming attempts in response to a failure in verifying the state of at least one of the selected memory cells.
15. The electronic system of claim 14 wherein the memory control signals comprises a programming command, a read command, address data and data to be stored in the memory device.
16. The electronic system of claim 15 wherein the memory device is further adapted to set a programming counter in response to receiving a programming command.
17. The electronic system of claim 16 wherein the programming counter is set to 1 in response to receiving a programming command.
18. The electronic system of claim 16 wherein the programming counter is incremented in response to a failure in verifying the state of one of the selected memory cells.
19. The electronic system of claim 18 wherein a programming error has occurred if the programming counter equals a predetermined maximum number of programming attempts.
20. The electronic system of claim 14 wherein the memory control circuitry is further adapted to raise the bias on unselected wordlines for a programming verify operation from the predetermined negative voltage to ground potential.