Patent Assignment
Reel/Frame 054372/0281
Release of Security Interest
Recorded: 2020-11-10
Pages: 74
Assignor
CPPIB CREDIT INVESTMENTS INC.
Executed: 2020-10-28
Assignee
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
515 LEGGET DRIVE, SUITE 704, OTTAWA, K2K 3G4, CANADA
Covered Properties
(51)
Reduced Area Sense Amplifier Isolation Layout in a Dynamic Ram Architecture
Patent:
6,480,407 →
Application:
08/519,504 →
Selective Method to Form Roughened Silicon
Patent:
6,355,536 →
Application:
09/093,217 →
Method and Apparatus for Inspecting Wafers
Aluminum-Beryllium Alloys for Air Bridges
Patent:
6,509,590 →
Application:
09/119,355 →
A Semiconductor Circuit Design Method for Employing Spacing Constraints and Circuits Thereof
Patent:
6,223,331 →
Application:
09/126,877 →
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Patent:
6,271,590 →
Application:
09/138,811 →
Surface Cleaning Apparatus and Method
Patent:
6,273,100 →
Application:
09/141,384 →
Device and Method for Repairing a Semiconductor Memory
Patent:
6,199,177 →
Application:
09/143,283 →
Diffusion Barrier Layers and Methods of Forming Same
Patent:
6,323,081 →
Application:
09/146,866 →
Gapped-Plate Capacitor
Patent:
6,018,175 →
Application:
09/148,032 →
Methods and Solutions for Cleaning Polished Aluminum-Containing Layers, Methods for Making Metallization Structures, and the Structures Resulting from These Methods
Patent:
6,265,781 →
Application:
09/153,053 →
Capacitor Electrode for Integrating High K Materials
Patent:
6,750,500 →
Application:
09/225,887 →
Gapped-Plate Capacitor
Patent:
6,316,326 →
Application:
09/229,857 →
Method of Forming Dram Trench Capacitor with Metal Layer Over Hemispherical Grain Polysilicon
Methods of Forming Capacitors
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Patent:
6,281,543 →
Application:
09/386,833 →
Deadhesion Method and Mechanism for Wafer Processing
Patent:
6,316,363 →
Application:
09/387,429 →
Chemical Treatment of Semiconductor Substrates
Patent:
6,395,647 →
Application:
09/388,570 →
Apparatus and Method for Increasing Test Flexibility of a Memory Device
Patent:
6,141,276 →
Application:
09/389,680 →
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Patent:
7,253,076 →
Application:
09/590,795 →
Gapped-Plate Capacitor
Patent:
6,498,363 →
Application:
09/652,837 →
Surface cleaning apparatus
Patent:
6,269,511 →
Application:
09/679,806 →
Apparatus and Method for Increasing Test Flexibility of a Memory Device
Patent:
6,459,635 →
Application:
09/703,360 →
Capacitor Constructions
Capacitor Structures
Sequential Pulse Deposition
Rhodium-Rich Oxygen Barriers
Method for Forming Raised Structures by Controlled Selective Epitaxial Growth of Facet Using Spacer
Semiconductor Circuit Design Methods, Semiconductor Processing Methods and Integrated Circuitry
Methods and Solutions for Cleaning Polished Aluminum-Containing Layers, Methods for Making Metallization Structures, and the Structures Resulting from These Methods
Capacitor Electrode for Integrating High K Materials
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Metal Local Interconnect Self-Aligned Source Flash Cell
Deadhesion Method and Mechanism for Wafer Processing
Methods for Forming and Integrated Circuit Structures Containing Ruthenium and Tungsten Containing Layers
Graded Layer for Use in Semiconductor Circuits and Method for Making Same
Double Layer Electrode and Barrier System on Hemispherical Grain Silicon for Use with High Dielectric Constant Materials and Methods for Fabricating the Same
Methods and Apparatus for Duty Cycle Control
Gapped-Plate Capacitor
Flash Memory Device with Improved Programming Performance
Gapped-Plate Capacitor
Data Path Having Grounded Precharge Operation and Test Compression Capability
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
Gapped-Plate Capacitor
Data Path Having Grounded Precharge Operation and Test Compression Capability
Flash Memory Device with Improved Programming Performance
Sequential Pulse Deposition
Flash Memory Device with Improved Programming Performance
Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow
A Vertical Transistor Having a Vertical Gate Structure Having a Top or Upper Surface Defining a Facet Formed Between a Vertical Source and a Vertical Drain.
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
U.S. Intellectual Property Security Agreement (for Non-U.S. Grantors) - Short Form
Jan 10, 2012
From: 658276 N.B. LTD.; 658868 N.B. INC.; MOSAID TECHNOLOGIES INCORPORATED
To: ROYAL BANK OF CANADA
Reel/Frame 027512/0196 →
Change of Name
Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
Release of Security Interest
Aug 7, 2014
From: ROYAL BANK OF CANADA
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.; CONVERSANT IP N.B. 868 INC.; CONVERSANT IP N.B. 276 INC.
Reel/Frame 033484/0344 →
Change of Address
Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
U.S. Patent Security Agreement (for Non-U.S. Grantors)
Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
Amended and Restated U.S. Patent Security Agreement (for Non-U.S. Grantors)
Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
Release of U.S. Patent Agreement (for Non-U.S. Grantors)
Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →