Granted Patent B2

US 7,038,945 · App. 10/841,785 · Granted May 2, 2006

Abstract

Claims (35)

1. A method for programming a flash memory cell of a memory array having bitlines and wordlines, the method comprising:

pulsing a bitline, coupled to the flash memory cell, with a programming pulse having a first predetermined voltage;

biasing a selected wordline, coupled to the flash memory cell, to a second predetermined voltage; and

biasing unselected wordlines to a predetermined negative voltage.

2. The method of claim 1 wherein the predetermined negative voltage is substantially in a range of −0.1 to −8V.

3. The method of claim 1 wherein the first predetermined voltage is substantially in a range of 3–6V.

4. The method of claim 1 wherein the second predetermined voltage is substantially in a range of 6–12V.

5. The method of claim 1 and further including verifying the programmed flash memory cell.

6. The method of claim 5 wherein verifying comprises returning the unselected wordlines from the predetermined negative voltage to a ground potential.

7. The method of claim 1 wherein the memory array is connected in a NOR architecture.

8. A method for programming a plurality of flash memory cells of a memory array, the plurality of memory cells each having a drain connection that is coupled to a different bitline of a plurality of bitlines of the memory array and each flash memory cell having a control gate that is coupled to a selected wordline, the method comprising:

pulsing each bitline of the plurality of bitlines with a first predetermined voltage in a respective manner as each flash memory cell of the plurality of flash memory cells that is coupled to the respective bitline is to be programmed;

biasing, to a second predetermined voltage, the selected wordline; and

biasing unselected wordlines of the memory array to a predetermined negative voltage.

9. The method of claim 8 wherein the memory array is comprised of a NOR architecture.

10. The method of claim 8 wherein the predetermined negative voltage is substantially in a range of −0.1 to −8V.

11. A method for programming a plurality of flash memory cells of a memory array, the plurality of memory cells each having a drain connection that is coupled to a bitline of the memory array and each flash memory cell having a control gate that is coupled to a selected wordline of a plurality of wordlines, the method comprising:

pulsing the bitline with a programming pulse having a first predetermined voltage;

biasing, to a second predetermined voltage, the selected wordline of the plurality of wordlines; and

biasing the remaining wordlines of the plurality of wordlines to a predetermined negative voltage.

12. The method of claim 11 wherein the predetermined negative voltage is substantially in a range of −0.1 to −8V, the first predetermined voltage is substantially in a range of 3–6V, and the second predetermined voltage is substantially in a range of 6–12V.

13. The method of claim 11 and further including verifying each programmed flash memory cell.

14. The method of claim 13 wherein verifying each programmed flash memory cell comprises raising each remaining wordline to ground potential for a read operation to be performed.

15. A method for programming a plurality of flash memory cells of a memory array, the plurality of memory cells each having a drain connection that is coupled to a bitline of the memory array and each flash memory cell having a control gate that is coupled to a selected wordline of a plurality of wordlines, the method comprising:

receiving a program command;

receiving an address of a cell to be programmed with data to be programmed;

biasing unselected wordlines to a negative voltage;

biasing a selected wordline, in response to the address, to a wordline programming voltage;

providing a program pulse on the bitline to program the cell to a desired state in response to the data to be programmed, the program pulse having a bitline programming voltage;

biasing the selected wordline to a wordline verify voltage;

biasing unselected wordlines to ground potential;

biasing the bitline to a bitline verify voltage;

if the cell's desired state is not substantially equivalent to the data to be programmed, repeating program attempts for a predetermined number of attempts.

16. The method of claim 15 and further including indicating an error condition if the predetermined number of attempts has been reached and the cell's desired state does not substantially equal the data to be programmed.

17. The method of claim 15 and further including indicating a successful program operation if the cell's desired state is substantially equivalent to the data to be programmed.

Assignments (12)