Gapped-plate capacitor
View Patent ↗In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.
1. A semiconductor device, comprising:
a first electrode;
an insulative material over said first electrode;
a second electrode, further comprising:
a first layer over said insulative material and having a first opening, and
a second layer over said first layer; and
a first portion of dielectric material spanning said first opening.
2. The semiconductor device of claim 1 , wherein said second layer has a second opening aligned with said first opening; and said semiconductor device further comprises a second portion of dielectric material spanning said second opening.
3. The semiconductor device of claim 2 , wherein said insulative material, said first portion of dielectric material, and said second portion of dielectric material are of the same material.
4. A semiconductor device, comprising:
a substrate; and
a conductive plate within a plate site, generally over said substrate and separated from said substrate by an insulator, wherein said conductive plate and said substrate define:
a parallel capacitance region within said plate site, and
a fringe capacitance region within said plate site and non-intersecting with said substrate.
5. The semiconductor device in claim 4 , wherein said conductive plate has a bore within said plate site, and said bore and said substrate define said fringe capacitance region.
6. The semiconductor device in claim 5 , wherein said substrate comprises a first diffusion region within said plate site, and said bore and said first diffusion region define said fringe capacitance region.
7. The semiconductor device in claim 6 , wherein said substrate comprises a second diffusion region external to said plate site, and said conductive plate and said second diffusion region define an additional fringe capacitance region external to said plate site.
8. The semiconductor device in claim 7 , wherein said plate site is defined by an in-process mask pattern that excludes an opening corresponding to said bore.
9. A semiconductor device, comprising:
a first capacitor electrode;
a second capacitor electrode generally conformal to said first capacitor electrode
and defining a nonconformity with respect to said first capacitor electrode,
wherein said nonconformity is configured to generate fringe capacitance in cooperation with said first capacitor electrode; and
a dielectric layer interposed between said first capacitor electrode and said second capacitor electrode.