Delay locked loop implementation in a synchronous dynamic random access memory
View Patent ↗A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
1. A synchronous memory comprising:
a memory array;
a clock input configured to receive a clock input signal;
a delay locked loop configured to provide an output clock signal derived from the received clock input signal, the output clock signal having an adjusted delay, wherein the delay locked loop comprises a tapped delay line including taps configured to provide plural outputs; and
data output circuitry between the memory array and an output terminal, the data output circuitry configured to be enabled by the output clock signal to output data synchronously with the output clock signal in normal operation, the synchronous memory having a low power mode and being configured to keep an adjusted delay setting for use on return to normal operation by preserving a last tap position when entering the low power mode.
2. The synchronous memory of claim 1 further comprising: a comparator configured to compare the output clock signal with the clock input signal in determining the adjusted delay.
3. The synchronous memory of claim 1 , wherein the low power mode comprises a power down mode.
4. The synchronous memory of claim 1 , wherein the low power mode comprises a standby state.
5. The synchronous memory of claim 1 , wherein the delay locked loop locks the output clock signal to the clock input signal over a period of time upon start-up and locks the output clock signal to the clock input signal faster using the kept adjusted delay upon exiting the low power mode.
6. The synchronous memory of claim 1 , wherein the delay locked loop is configured to:
lock the output clock signal to the clock input signal over a period of time upon start-up; and
lock the output clock signal to the clock input signal faster using the kept adjusted delay setting upon exiting the low power mode.
7. The synchronous memory of claim 1 , wherein the delay locked loop is further configured to adjust the delay of the output clock signal based on the kept adjusted delay setting.
8. The synchronous memory of claim 1 , wherein the memory array comprises a synchronous dynamic random access memory (SDRAM) array.
9. The synchronous memory of claim 1 wherein the tapped delay line comprises a series of inverters.
10. The synchronous memory of claim 2 , wherein the delay locked loop further comprises a delay model that is configured to delay the output clock signal applied to the comparator.