Low power memory architecture
View Patent ↗A memory architecture and circuits for minimizing current leakage in the memory array. Subdivisions of the memory array each have local power grids that can be selectively connected to power supplies, such that only an accessed subdivision will receive power to execute the memory access operation. The memory array can further include databuses which are precharged to one voltage during idle times and a second voltage during active read cycles, which reduces leakage current in datapath circuitry connected to the databuses within the memory array blocks.
1. A datapath circuit comprising:
a databus;
a precharge circuit for selectively precharging the databus to a first voltage during an idle period and a second voltage in an active period; and,
a plurality of data transfer circuits each selectable for connecting the databus to the first voltage in response to data in the active period.
2. The datapath circuit of claim 1 , wherein the precharge circuit includes
a pull-up circuit for precharging the databus to the second voltage in the active period, and,
a pull-down circuit for precharging the databus to the first voltage during the idle period.
3. The datapath circuit of claim 1 , wherein the databus includes true and complementary datalines.
4. The datapath circuit of claim 3 , wherein the pull-up circuit includes a first pull-up transistor pair for connecting the true dataline and the complementary dataline to the second voltage.
5. The datapath circuit of claim 4 , wherein the pull-down circuit includes a pull-down transistor pair for connecting the true dataline and the complementary dataline to the first voltage.
6. A method for low power datapath operation comprising:
a) precharging a databus pair from a first voltage to a second voltage in an active period;
b) driving one of the databus pair to the first voltage in response to data during the active period; and,
c) precharging the databus pair to the first voltage in an idle period after the active period has ended.
7. The method of claim 6 , wherein the step of precharging the databus pair to the second voltage includes disabling pull-down down transistors coupled between the databus pair and the first voltage, before enabling pull-up transistors coupled between the databus pair and the second voltage.
8. The method of claim 7 , wherein the step of precharging the databus pair to the first voltage includes disabling the pull-up transistors before enabling the pull-down transistors.