Method and apparatus for integrated circuit design with library cells
View Patent ↗Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
1. A cell library, comprising:
one or more cells having one or more virtual buses, the one or more cells for an integrated circuit design, wherein the one or more virtual buses comprise:
a plurality of ports representing a common power signal on a first layer, and each of said plurality of ports are positioned on each of said one or more cells without reference to a construction grid and wherein said plurality of ports are connected on a second layer with an absence of connections between said plurality of ports on said first layer.
2. The library of claim 1 , wherein the common power signal includes a fixed voltage signal.
3. The library of claim 1 , wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
4. The library of claim 1 , wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
5. The library of claim 1 , wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
6. The library of claim 1 , wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
7. The library of claim 1 , wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
8. The library of claim 1 , wherein the one or more cells includes at least one standard cell.
9. A cell library, comprising:
one or more cells having one or more virtual buses, the one or more cells for an integrated circuit design, wherein the one or more virtual buses comprise:
a plurality of ports representing a common power signal on a same layer, the said plurality of ports are coupled together via one or more electrical paths, and each of said plurality of ports are positioned on each of said one or more cells without reference to a construction grid and wherein said one or more electrical paths are on a layer other than said same layer of said plurality of ports and there is an absence of connection between said plurality of ports on said layer of said ports.
10. The library of claim 9 , wherein the common power signal includes a fixed voltage signal.
11. The library of claim 9 , wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
12. The library of claim 9 , wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
13. The library of claim 9 , wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
14. The library of claim 9 , wherein an integrated circuit of the integrated circuit design is formed by a silicon-on-Insulator process.”
15. The library of claim 9 , wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.