Flash memory program inhibit scheme
View Patent ↗A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.
1. A memory array having a NAND string coupled between a bitline and a sourceline precharged to a program inhibit voltage during a program operation for inhibiting programming of a selected memory cell, comprising:
a string select transistor driven to a voltage level for coupling the program inhibit voltage of the bitline to all memory cells of the NAND string;
lower memory cells between the selected memory cell and the sourceline driven to a first pass voltage in a first time period;
upper memory cells between the selected memory cell and the bitline driven to a second pass voltage in the first time period for precharging the upper memory cell channels to a primary boosted voltage; and
a selected memory cell driven from a third pass voltage in the first time period for precharging the selected memory cell channel to the primary boosted voltage, to a programming voltage greater than the first pass voltage in a second time period following the first time period.
2. The memory array of claim 1 , wherein the first pass voltage, the second pass voltage, and the third pass voltage are the same.
3. The memory array of claim 1 , wherein the third pass voltage is less than the first pass voltage.
4. The memory array of claim 1 , wherein the upper memory cells include an upper memory cell adjacent the selected memory cell electrically turned off during the second time period.
5. The memory array of claim 4 , wherein the upper memory cell is driven to a decoupling voltage less than the second pass voltage and greater than 0V in the second time period.
6. The memory array of claim 1 , wherein the lower memory cells include a lower memory cell adjacent the selected memory cell electrically turned off during the second time period.
7. The memory array of claim 6 , wherein the lower memory cell is driven to a decoupling voltage less than the second pass voltage and greater than 0V in the second time period.
8. The memory array of claim 1 , wherein the string select transistor is driven to the program inhibit voltage before the first time period for a duration extending into the second time period.
9. The memory array of claim 1 , wherein the string select transistor driven to the program inhibit voltage before the first time period.
10. The memory array of claim 9 , wherein the string select transistor is driven to a leakage minimization voltage in the first time period for a duration extending into the second time period.
11. The memory array of claim 6 , wherein the first pass voltage is less than the second pass voltage, and greater than a threshold voltage corresponding to a programmed memory cell.
12. The memory array of claim 11 , wherein the lower memory cell adjacent the selected memory cell is driven to 0V in the second time period.
13. The memory array of claim 1 , wherein the first pass voltage is greater than the second pass voltage.
14. The memory array of claim 13 , wherein the upper memory cells include a first upper memory cell adjacent the selected memory cell and a second upper memory cell adjacent the first upper memory cell, the first upper memory cell electrically turning off during the second time period when the second upper memory cell is driven to a fourth pass voltage greater than the second pass voltage.
15. The memory array of claim 14 , wherein the lower memory cells include a first lower memory cell adjacent the selected memory cell and a second lower memory cell adjacent the first lower memory cell, the first lower memory cell electrically turning off during the second time period.
16. The memory array of claim 15 , wherein the first lower memory cell is driven to 0V.
17. The memory array of claim 16 , wherein the selected memory cell is driven to the programming voltage after a predetermined delay after the first lower memory cell is driven towards 0V.