Apparatus for flexible deactivation of word lines of dynamic memory modules and method therefor
View Patent ↗An apparatus and a method are proposed, which can be used to delay a deactivation of a row address in the event of repeated access to a bank of an RLDRAM memory module.
1. A reduced latency dynamic random access memory (RLDRAM) module, comprising:
an activation circuit configured to assert a row activate signal to activate a row accessed by a memory access request received by the module, assert a column activate signal to activate a column accessed by the memory access request, de-assert the row activate signal after a defined activation time duration if the activated row is not accessed again within the defined time duration, and delay de-asserting the row activate signal if the activated row is accessed within the defined activation time duration.
2. The module of claim 1 , wherein the activation circuit is further configured to:
de-assert the column activate signal; and
if the activated row is accessed within the defined activation time, re-assert the column activate signal prior to de-asserting the row activate signal.
3. The module of claim 1 , wherein the activation circuit comprises:
a logic gate for generating a pulsed signal in response to a bank select signal and an access signal applied to inputs thereof;
a first bistable multivibrator configured to assert the row activate signal in response to receiving the pulsed output signal generated by the logic gate;
a first delay element configured to receive the pulsed signal generated by the logic gate at a start input and, in response, generate a first trigger signal a first delay period thereafter; and
a second delay element configured to receive the first trigger signal at a start input and, in response, generate a reset signal after a second delay period to reset the first multistate vibrator in order to de-assert the row activate signal, unless another pulsed signal generated by the logic gate is received at a reset input of the second delay element prior to expiration of the second delay period.
4. A reduced latency dynamic random access memory (RLDRAM) module, comprising:
a row address decoder for selecting a row of memory cells within a bank of memory cells based on a row address;
a column address decoder for selecting a column of memory cells in a row selected by the row address decoder, based on a column address;
separate busses for applying the row address to the row address decoder and the column address to the column address decoder; and
an activation circuit configured to assert a row activate signal to activate the row selected by the row address decoder, assert a column activate signal to activate the column selected by the column address decoder, de-assert the row activate signal after a defined activation time duration if the activated row is not accessed again within the defined time duration, and delay de-asserting the row activate signal if the activated row is accessed within the defined time duration.
5. The memory module of claim 4 , wherein the activation circuit comprises:
a logic gate for generating a pulsed signal in response to a bank select signal and an access signal applied to inputs thereof;
a first bistable multivibrator configured to assert the row activate signal in response to receiving the pulsed output signal generated by the logic gate;
a first delay element configured to receive the pulsed signal generated by the logic gate at a start input and, in response, generate a first trigger signal a first delay period thereafter; and
a second delay element configured to receive the first trigger signal at a start input and, in response, generate a reset signal after a second delay period to reset the first multistate vibrator in order to de-assert the row activate signal, unless another pulsed signal generated by the logic gate is received at a reset input of the second delay element prior to expiration of the second delay period.
6. The memory module of claim 5 , wherein the first and second delay periods define the defined activation time duration.
7. The memory module of claim 5 , wherein the activation circuit further comprises:
a second bistable multivibrator configured to assert the column activate signal a third time period after the row activate signal is asserted by the first bistable multivibrator.
8. The memory module of claim 7 , wherein the activation circuit further comprises:
a first pulse generator configured to generate a pulse in response to the row activate signal asserted by the first bistable multivibrator; and
a third delay element configured to receive the pulse generated by the first pulse generator and, in response, generate a set signal after the third delay period to set the second bistable multivibrator to assert the column activate signal.
9. The memory module of claim 8 , wherein the activation circuit further comprises:
a second pulse generator configured to generate a pulse in response to the column activate signal asserted by the second bistable multivibrator; and
a fourth delay element configured to receive the pulse generated by the second pulse generator and, in response, generate a reset signal after a fourth delay period to reset the second bistable multivibrator to de-assert the column activate signal.
10. A method for accessing of a row of memory cells in a bank of memory cells of a dynamic memory module with random memory cell access, comprising:
applying a row address to a row address decoder to select a row of memory cells and applying a column address to a column address decoder to select a column of memory cells within the selected row;
asserting a row activate signal to activate the row of memory cells selected by the row address decoder;
asserting a column activate signal to activate the column of memory cells selected by the column address decoder;
de-asserting the row activate signal after a defined activation time duration if the activated row is not accessed within the defined activation time duration; and
delaying de-assertion of the row activate signal beyond the defined activation time duration if the activated row is accessed within the defined time duration.
11. The method of claim 10 , wherein delaying de-assertion of the row activate signal comprises keeping the row activate asserted for at least the defined time duration after the activated row is accessed again.
12. The method of claim 10 , comprising asserting the column activate signal to activate different columns of memory cells within the same row of memory cells while the row activate signal is asserted.
13. A method for accessing memory cells of a reduced latency dynamic random access memory (RLDRAM) module, comprising:
receiving a first row address identifying, within a bank of memory cells of the module, a first row of memory cells and a first column address identifying a first column of memory cells within the first row to be accessed;
asserting a first row activate signal to activate the first row of memory cells;
asserting a first column activate signal to activate the first column of memory cells; and
prior to de-asserting the first row activate signal:
again receiving the first row address;
receiving a second column address identifying a second column of memory cells within the first row to be accessed; and
asserting a second column activate signal to activate the second column of memory cells.
14. The method of claim 13 , further comprising, prior to de-asserting the first row activate signal:
again receiving the first row address;
receiving a third column address identifying a third column of memory cells within the first row to be accessed; and
asserting a third column activate signal to activate the second column of memory cells.
15. The method of claim 13 , further comprising de-asserting the row activate signal if a defined time period expires without again receiving the first row address.
16. A method for accessing memory cells of a reduced latency dynamic random access memory (RLDRAM) module, comprising:
receiving a first memory access request to access a first row of memory cells in the module;
asserting a row activate signal to activate the first row of memory cells; and
prior to de-asserting the row activate signal, allowing multiple columns within the first row to be accessed.
17. The method of claim 16 , wherein allowing multiple columns within the first row to be accessed comprises:
asserting a column activate signal to access a first column of memory cells identified with the first memory access request;
de-asserting the column activate signal;
receiving a second memory access request to again access the first row of memory cells in the module; and
re-asserting the column activate signal to access a second column of memory cells identified with the second memory access request.
18. The method of claim 16 , further comprising receiving the row address of the first row and a column address of the first column on separate buses.
19. The method of claim 16 , wherein asserting the row activate signal to activate the first row of memory cells comprises:
asserting the row activate signal for a defined row activation time period after the first memory access request if no subsequent memory access requests to access the first row of memory addresses are received within the defined row activation time period.
20. The method of claim 19 , wherein asserting the row activate signal to activate the first row of memory cells further comprises:
delaying de-asserting the row activate signal for the defined row activation time period after subsequent memory access requests to access the first row of memory addresses are received within the defined row activation time period.