Delay locked loop implementation in a synchronous dynamic random access memory
View Patent ↗A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period or the clock input signal.
1. A synchronous dynamic random access memory (SDRAM) comprising:
an SDRAM memory array;
an SDRAM data output circuit;
a clock signal; and
a delay locked loop (DLL) having an adjustable delay line for generating a driving clock signal from the clock input signal, the driving clock signal to be applied to the SDRAM data output circuit, the adjustable delay line being a tapped delay line and the DLL being used and not used, as the clock input signal is maintained, in response to external control, wherein taps provide plural outputs of the delay line and a comparator in the DLL determined one of the tap outputs that forms the driving clock signal.
2. The SDRAM of claim 1 wherein the DLL is disabled when not used as a clock source for enabling data output.
3. A synchronous dynamic random access memory (SDRAM) comprising:
a delay locked loop (DLL) having an adjustable delay for producing a driving clock signal in response to a clock input signal, the DLL being used and not used, as a clock source for enabling data output, as the clock input signal is maintained, in response to external control;
an SDRAM array; and
an SDRAM data output circuit for outputting data from the SDRAM array to an output terminal, the SDRAM data output circuit being enabled in response to the driving clock signal where the DLL is used as a clock source for enabling data output and the SDRAM data output circuit being enabled by another clock signal when the DLL is not used as a clock source for enabling data output.
4. The SDRAM of claim 3 wherein the adjustable delay comprises a tapped delay line including taps for providing plural outputs thereof.
5. The SDRAM of claim 3 wherein the DLL is a delay line and comprises a comparator for comparing the driving clock signal with the clock input signal to determine the delay by the delay line.
6. The SDRAM of claim 5 wherein the comparator is capable of minimizing the delay between the clock input signal and the driving clock signal.
7. The SDRAM of claim 3 wherein the SDRAM data output circuit is a data output buffer.
8. The SDRAM of claim 3 wherein the external control is provided by a bit having two logic states, one of the two states causing the DLL to be not used as a clock source for enabling SDRAM the data output circuit.
9. The SDRAM of claim 3 wherein settings of the adjustable delay are maintained when the delay locked loop is not used as a clock source for enabling data output.
10. The SDRAM of claim 3 wherein the another clock signal is a buffered version of the clock input signal.
11. A method of providing a clock to a synchronous dynamic random access memory (SDRAM) comprising:
generating a driving clock signal in the SDRAM from a clock input signal through a delay locked loop (DLL) having an adjustable delay line, the adjustable delay line being a tapped delay line; and
using external control, discontinuing use of the delay locked loop as the clock input signal is maintained,
wherein taps of the tapped delay line provide plural outputs of the delay line and one of the tap outputs is determined by a comparator in the DLL to form the driving clock signal.
12. A method of providing a clock to a synchronous dynamic random access memory (SDRAM), the method comprising:
providing a driving clock signal in response to a clock input signal through a delay locked loop (DLL) having an adjustable delay;
enabling an SDRAM data output circuit with the driving clock signal to output data from an SDRAM array to an output terminal; and
using external control, discontinuing use of the DLL as a clock source for enabling SDRAM the data output circuit, as the clock input signal is maintained, and enabling the SDRAM data output circuit with another clock signal.
13. The method of claim 12 wherein the adjustable delay comprises a tapped delay line having taps, the step of providing comprising providing plural outputs from taps of the tapped delay line.
14. The method of claim 12 wherein the adjustable delay is a delay line and the step of providing further comprises comparing the driving clock signal with the clock input signal to determine the adjusted delay by the delay line.
15. The method of claim 14 wherein the step of comparing comprises minimizing the delay between the clock input signal and the driving clock signal.
16. The method of claim 12 wherein the SDRAM data output circuit is a data output buffer.
17. The method of claim 12 wherein the external control is based on a condition of the SDRAM.
18. The method of claim 12 wherein the external control is applied during a start-up of the DLL.
19. The method of claim 12 wherein the external control is provided in response to a bit having two logic states, one of the two states causing the DLL to be not used as a clock source for enabling SDRAM the data output circuit.
20. The method of claim 12 wherein settings of the adjustable delay are maintained when the delay locked loop is not used as a clock source for enabling the SDRAM data output circuit.
21. The method of claim 12 wherein the another clock signal is a buffered version of the clock input signal.
22. The method of claim 12 wherein the DLL is disabled when its use is discontinued.