Multi-level cell access buffer with dual function
View Patent ↗An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.
1. An apparatus for writing to a non-volatile memory, the apparatus comprising:
a single-ended input for receiving a single-ended input signal having an input bit to be written to the memory;
first and second latches, the first latch having a double-ended input, for receiving a double-ended input signal containing the input bit, the second latch being configured to latch a value read from a lower page of a memory location of the non-volatile memory; and
a processor for producing a complement of the single-ended input signal, the double-ended input signal comprising the complement of the single-ended input signal and the single-ended input signal.
2. A method for writing to a non-volatile memory, the method comprising:
receiving a single-ended input signal having an input bit to be written to the memory;
producing a complement of the single-ended input signal using an input inverter comprising a driving inverter, the complement of the single-ended input signal and the single-ended input signal in combination forming a double-ended input signal;
latching the input bit into a first latch having a double-ended input; and
latching a value read from a lower page of a memory location of the non-volatile memory into a second latch.
3. A system comprising:
a non-volatile memory structure;
an access buffer for writing to the non-volatile memory structure, the access buffer comprising:
a latch circuit having a first input and a second input, the latch circuit comprising an inverter having the second input;
the access buffer having a first mode of operation in which a first signal received at the first input is latched by the latch circuit;
the access buffer having a second mode of operation in which a second signal received at the second input is inverted by the inverter.
4. The system of claim 3 further comprising a circuit for:
enabling the first input while in the first mode of operation, disabling the second input while in the first mode of operation, disabling the first input while in the second mode of operation, and enabling the second input while in the second mode of operation.
5. The system of claim 4 wherein the circuit for enabling the first input while in the first mode of operation, disabling the second input while in the first mode of operation, disabling the first input while in the second mode of operation, and enabling the second input while in the second mode of operation comprises:
a first pass circuit having a first state in which the first signal is passed to the first input, and having a second state in which the first signal is prevented from being passed to the first input;
a second pass circuit having a first state in which the second signal is prevented from being passed to the second input, and having a second state in which the second signal is passed to the second input.
6. The system of claim 5 further comprising:
a first control input on the first pass circuit for controlling the first pass circuit to be in a selected one of the first state and the second state of the first pass circuit;
a second control input on the second pass circuit for controlling the second pass circuit to be in a selected one of the first state and the second state of the second pass circuit.
7. The system of claim 6 further comprising:
a control circuit configured to generate a first control signal for the first control input so as to control the first pass circuit to be in the first state during the first mode of operation and to be in the second state during the second mode of operation;
the control circuit further configured to generate a second control signal for the second control input so as to control the second pass circuit to be in the first state during the first mode of operation and to be in the second state during the second mode of operation.
8. The system of claim 7 further comprising:
a third pass circuit having a first state in which a signal at an output of the driving inverter is prevented from being passed on, and having a second state in which the signal at the output of the driving inverter is passed on;
a third control input on the third pass circuit for controlling the third pass circuit to be in a selected one of the first state and the second state of the first pass circuit.
9. The system of claim 8 wherein:
the control circuit is further configured to generate a third control signal to the third control input so as to control the third pass circuit to be in the first state during the first mode of operation and to be in the second state during the second mode of operation.
10. The system of claim 9 wherein the second input signal and the signal at the output of the driving inverter together constitute a double ended input signal during the second mode of operation.
11. The system of claim 3 wherein the non-volatile memory situation is configured for multi-level cell programming;
wherein the first signal at the first input comprises a value read from a lower page of a memory situation location of the non-volatile memory for the purpose of setting a validation threshold for a multi-level cell program operation.
12. The system of claim 11 wherein the second signal at the second input comprises an input signal containing a bit to be written to the non-volatile memory.
13. The system of claim 3 wherein the second signal at the second input comprises an input signal containing a bit to be written to the non-volatile memory.
14. The system of claim 3 wherein the non-volatile memory structure comprises a memory cell array.
15. The system of claim 14 wherein the memory cell array comprises a flash memory cell string including a plurality of floating gate memory cells connected in-series, the series connected memory cells being coupled to a bitline, the memory cells being coupled to respective wordlines.
16. The system of claim 3 wherein the non-volatile memory structure comprises a flash memory, the access buffer functioning as a page buffer for the flash memory.
17. The system of claim 3 wherein the inverter comprises a driving inverter.