Dynamic random access memory and boosted voltage producer therefor
View Patent ↗A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.
1. A dynamic random access memory (DRAM) having storage cells for storing data, the data being refreshable in a sleep mode, the DRAM comprising:
a voltage producer configured to provide an output voltage to be used for operation of the DRAM, the voltage producer including a pump circuit configured to provide the output voltage in response to a plurality of enable signals, the pump circuit including a plurality of pump circuit segments wherein each of the pump circuit segments is selectively activatable in response to a respective one of the plurality of enable signals;
a voltage level detector configured to determine whether the output voltage reaches a predetermined level; and
a controller configured to provide the plurality of enable signals in response to a refresh time in the sleep mode; wherein the controller is configured to receive a plurality of refresh time signals representing the refresh time; and provide the plurality of enable signals for selectively activating one or more of the plurality of pump circuit segments to be activated according to the refresh time represented by the plurality of refresh time signals.
2. The DRAM as claimed in claim 1 , wherein each of the pump circuit segments comprises:
a pump circuit configured to pump the output voltage in response to an oscillation signal provided in the sleep mode.
3. The DRAM as claimed in claim 1 , wherein the voltage producer comprises:
a pump circuit configured to pump the output voltage to be used as at least one of a word bootstrapping voltage and a substrate bias voltage in the DRAM.
4. A method for producing a boosted voltage for a dynamic random access memory (DRAM) having storage cells for storing data, the data being refreshable in a sleep mode, the method comprising:
providing an output voltage to be used for operation of the DRAM;
determining whether the output voltage reaches a predetermined level to provide a determination result;
providing a plurality of enable signals in response to a refresh time when the DRAM is in the sleep mode; and
selectively activating each of a plurality of pump circuit segments in response to a respective one of the plurality of enable signals for producing the output voltage; wherein providing the plurality of enable signals comprises receiving a plurality of refresh time signals representing the refresh time; and providing the plurality of enable signals for selectively activating respective ones of the plurality of pump circuit segments according to the refresh time represented by the plurality of refresh time signals.
5. The method as claimed in claim 4 , wherein providing the output voltage comprises:
pumping the output voltage in response to an oscillation signal provided in the sleep mode.